Chapter 4
SYSTEMATIC YIELD - CHEMICAL
MECHANICAL POLISHING (CMP)
4.1 Introduction
The classical IC manufacturing process is divided into what is referred to as
“front end” processing and “backend” processing. The front end processing are
the steps associated with building the devices themselves (gates) while backend
processing refers to the interconnect steps that start at the level of contacting
the transistor terminals and then progressing through a vertical stack of metal
layers separated by layers of dielectric material. Wire segments in various metal
layers are connected vertically to one another through vias that are etched in
the dielectric layers for the purpose of such connectivity.
Aluminum interconnect was the standard metal used for IC manufacturing
for all technology nodes 130nm and above. Limitations associated with the
current carrying capability, high resistance, and metal migration of Aluminum
prompted the searchfor a replacement. Gold (Au), Silver (Ag), and Copper (Cu)
were the threecontenders; andCu emerged as the new standard on a combination
of high current carrying capability, low resistance, and cost. But, dealing with
Cu interconnect meant developing a totally different backend process namely
the Damascene and then the Dual Damascene processes. Since Cu cannot be
etched out using abrasive subtractive etching procedures as was used for Al,
metal sputtering was not an option. A patterned trench filled with Cu through
electroplating; and then etched in a columnar fashion are the basics of the
modern Dual Damascene processes (Dual Damascene processes with Al fills
were done first). Since this book is intended for the nano CMOS technology we
will completely skip the Aluminum alloy metallurgy used in 130nm and older
technology nodes and focus on Cu metallurgy currently used in all the nano
scale processes.
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