电子计价秤—PIC单片机汇编源程序资源-CSDN文库

共8个文件

pdf：8个

电子计价秤

技术资料

PIC单片机

汇编源程序

MPLAB

4星 · 超过85%的资源需积分: 10 30 浏览量 2009-09-04 14:19:32 上传评论收藏 1.32MB RAR 举报

资源推荐

资源详情

资源评论

收起资源包目录

PIC单片机汇编源代码.rar （8个子文件）

电子计价秤—PIC单片机汇编源代码

SCL_VA81.ASM.pdf 138KB

PIC62R.EQU.pdf 19KB

附录

HT1621.pdf 152KB

ICL7135.pdf 449KB

GBT7722-1995电子计价秤.pdf 153KB

24LC01.pdf 473KB

Scl_va Schematic.pdf 143KB

SCL_VA Readme.pdf 80KB

24AA01/24LC01B

Device Selection Table

Features:

• Single Supply with Operation Down to 1.7V for

24AAXX Devices, 2.5V for 24LCXX Devices

• Low-Power CMOS Technology:

- Read current 1 mA, max.

- Standby current 1 μA, max. (I-temp)

• 2-Wire Serial Interface, I

C™ Compatible

• Schmitt Trigger Inputs for Noise Suppression

• Output Slope Control to Eliminate Ground Bounce

• 100 kHz and 400 kHz Compatibility

• Page Write Time 3 ms, typical

• Hardware Write-Protect

• ESD Protection >4,000V

• More than 1 Million Erase/Write Cycles

• Data Retention >200 Years

• Factory programmable available

• Packages include 8-lead PDIP, SOIC, TSSOP,

DFN, MSOP, 5-lead SOT-23 and SC-70

• Pb-free and RoHS compliant

• Temperature ranges:

- Industrial (I): -40°C to +85°C

- Automotive (E): -40°C to +125°C

Description:

The Microchip Technology Inc. 24AA01/24LC01B

(24XX01*) is a 1 Kbit Electrically Erasable PROM. The

device is organized as one block of 128 x 8-bit memory

with a 2-wire serial interface. Low-voltage design

permits operation down to 1.7V with standby and active

currents of only 1 μA and 1 mA, respectively. The

24XX01 also has a page write capability for up to 8

bytes of data. The 24XX01 is available in the standard

8-pin PDIP, surface mount SOIC, TSSOP, 2x3 DFN and

MSOP packages, and is also available in the 5-lead

SOT-23 and SC-70 packages.

Package Types

Block Diagram

Part

Number

VCC

Range

Max. Clock

Frequency

Temp.

Ranges

24AA01 1.7-5.5 400 kHz

(1)

24LC01B 2.5-5.5 400 kHz I, E

Note 1: 100 kHz for V

CC <2.5V

VCC

SCL

SDA

PDIP, MSOP

SOIC, TSSOP

SCL

SDA

DFN

SCL

SDA

SOT-23/SC-70

SCL

Vss

SDA

Vcc

Note: Pins A0, A1 and A2 are not used by the 24XX01 (no

internal connections).

HV Generator

EEPROM

Array

Page Latches

YDEC

XDEC

Sense Amp.

Memory

Control

Logic

I/O

Control

Logic

I/O

SDA

SCL

VSS

R/W Control

1K I

™

Serial EEPROM

24AA01/24LC01B

1.0 ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings

(†)

VCC.............................................................................................................................................................................6.5V

All inputs and outputs w.r.t. V

SS ......................................................................................................... -0.3V to VCC +1.0V

Storage temperature ...............................................................................................................................-65°C to +150°C

Ambient temperature with power applied................................................................................................-40°C to +125°C

ESD protection on all pins ......................................................................................................................................................≥ 4kV

TABLE 1-1: DC CHARACTERISTICS

† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to

the device. This is a stress rating only and functional operation of the device at those or any other conditions

above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating

conditions for extended periods may affect device reliability.

DC CHARACTERISTICS

Industrial (I): T

A = -40°C to +85°C, VCC = +1.7V to +5.5V

Automotive (E): T

A = -40°C to +125°C, VCC = +2.5V to +5.5V

Param.

No.

Sym. Characteristic Min. Typ. Max. Units Conditions

D1 V

IH WP, SCL and SDA pins

—

————

D2 — High-level input voltage 0.7 VCC ——V—

D3 V

IL Low-level input voltage — — 0.3 VCC V—

D4 VHYS Hysteresis of Schmitt

Trigger inputs

0.05 VCC ——V(Note)

D5 V

OL Low-level output voltage — — 0.40 V IOL = 3.0 mA, VCC = 2.5V

D6 ILI Input leakage current ——±1μAVIN = VSS or VCC

D7 ILO Output leakage current ——±1μAVOUT = VSS or VCC

D8 CIN,

OUT

Pin capacitance

(all inputs/outputs)

——10pFVCC = 5.0V (Note)

A = 25°C, FCLK = 1 MHz

D9 ICC write Operating current —0.1 3mAVCC = 5.5V, SCL = 400 kHz

D10 I

CC read — 0.05 1 mA —

D11 ICCS Standby current —

—

0.01

—

μΑ

Industrial

Automotive

SDA = SCL = V

WP = VSS

Note: This parameter is periodically sampled and not 100% tested.

24AA01/24LC01B

TABLE 1-2: AC CHARACTERISTICS

AC CHARACTERISTICS

Industrial (I): T

A = -40°C to +85°C, VCC = +1.7V to +5.5V

Automotive (E): T

A = -40°C to +125°C, VCC = +2.5V to +5.5V

Param.

No.

Sym. Characteristic Min. Typ. Max. Units Conditions

CLK Clock frequency —

—

400

100

kHz 2.5V ≤ VCC ≤ 5.5V

1.7V ≤ V

CC < 2.5V (24AA01)

HIGH Clock high time 600

4000

—

ns 2.5V ≤ VCC ≤ 5.5V

1.7V ≤ V

CC <2.5V (24AA01)

3TLOW Clock low time 1300

4700

—

ns 2.5V ≤ VCC ≤ 5.5V

1.7V ≤ V

CC < 2.5V (24AA01)

4TR SDA and SCL rise time

(Note 1)

—

300

1000

ns 2.5V ≤ VCC ≤ 5.5V

1.7V ≤ V

CC < 2.5V (24AA01)

F SDA and SCL fall time — —

—

300 ns (Note 1)

HD:STA Start condition hold time 600

4000

—

ns 2.5V ≤ VCC ≤ 5.5V

1.7V ≤ V

CC < 2.5V (24AA01)

7TSU:STA Start condition setup

time

600

4700

—

ns 2.5V ≤ VCC ≤ 5.5V

1.7V ≤ V

CC < 2.5V (24AA01)

HD:DAT Data input hold time 0 —

—

—ns(Note 2)

SU:DAT Data input setup time 100

250

—

ns 2.5V ≤ VCC ≤ 5.5V

1.7V ≤ V

CC < 2.5V (24AA01)

10 TSU:STO Stop condition setup

time

600

4000

—

ns 2.5V ≤ VCC ≤ 5.5V

1.7V ≤ V

CC < 2.5V (24AA01)

11 T

AA Output valid from clock

(Note 2)

—

900

3500

ns 2.5V ≤ VCC ≤ 5.5V

1.7V ≤ V

CC < 2.5V (24AA01)

12 TBUF Bus free-time: Time the

bus must be free before

a new transmission can

start

1300

4700

—

ns 2.5V ≤ VCC ≤ 5.5V

1.7V ≤ V

CC < 2.5V (24AA01)

13 TOF Output fall time from VIH

minimum to V

maximum

20+0.1C

—

250

ns 2.5V ≤ V

CC ≤ 5.5V

1.7V ≤ V

CC < 2.5V (24AA01)

14 T

SP Input filter spike

suppression

(SDA and SCL pins)

— — 50 ns (Notes 1 and 3)

15 T

WC Write cycle time

(byte or page)

——5ms—

16 — Endurance 1M — — cycles 25°C, (Note 4)

Note 1: Not 100% tested. C

B = total capacitance of one bus line in pF.

2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region

(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.

3: The combined T

SP and VHYS specifications are due to new Schmitt Trigger inputs which provide improved

noise spike suppression. This eliminates the need for a

TI specification for standard operation.

4: This parameter is not tested but ensured by characterization. For endurance estimates in a specific

application, please consult the Total Endurance™ Model which can be obtained from Microchip’s web site

at www.microchip.com.

24AA01/24LC01B

FIGURE 1-1: BUS TIMING DATA

FIGURE 1-2: BUS TIMING START/STOP

SCL

SDA

OUT

Start Stop

SCL

SDA

24AA01/24LC01B

2.0 FUNCTIONAL DESCRIPTION

The 24XX01 supports a bidirectional, 2-wire bus and

data transmission protocol. A device that sends data

onto the bus is defined as transmitter, while defining a

device receiving data as a receiver. The bus has to be

controlled by a master device which generates the

Serial Clock (SCL), controls the bus access and

generates the Start and Stop conditions, while the

24XX01 works as slave. Both master and slave can

operate as transmitter or receiver, but the master

device determines which mode is activated.

3.0 BUS CHARACTERISTICS

The following bus protocol has been defined:

• Data transfer may be initiated only when the bus

is not busy.

• During data transfer, the data line must remain

stable whenever the clock line is high. Changes in

the data line while the clock line is high will be

interpreted as a Start or Stop condition.

Accordingly, the following bus conditions have been

defined (Figure 3-1).

3.1 Bus Not Busy (A)

Both data and clock lines remain high.

3.2 Start Data Transfer (B)

A high-to-low transition of the SDA line while the clock

(SCL) is high determines a Start condition. All

commands must be preceded by a Start condition.

3.3 Stop Data Transfer (C)

A low-to-high transition of the SDA line while the clock

(SCL) is high determines a Stop condition. All

operations must be ended with a Stop condition.

3.4 Data Valid (D)

The state of the data line represents valid data when,

after a Start condition, the data line is stable for the

duration of the high period of the clock signal.

The data on the line must be changed during the low

period of the clock signal. There is one clock pulse per

bit of data.

Each data transfer is initiated with a Start condition and

terminated with a Stop condition. The number of data

bytes transferred between the Start and Stop

conditions is determined by the master device and is,

theoretically, unlimited (although only the last sixteen

will be stored when doing a write operation). When an

overwrite does occur, it will replace data in a first-in

first-out (FIFO) fashion.

3.5 Acknowledge

Each receiving device, when addressed, is obliged to

generate an acknowledge after the reception of each

byte. The master device must generate an extra clock

pulse which is associated with this Acknowledge bit.

The device that acknowledges has to pull down the

SDA line during the acknowledge clock pulse in such a

way that the SDA line is stable low during the high

period of the acknowledge-related clock pulse. Of

course, setup and hold times must be taken into

account. During reads, a master must signal an end of

data to the slave by not generating an Acknowledge bit

on the last byte that has been clocked out of the slave.

In this case, the slave (24XX01) will leave the data line

high to enable the master to generate the Stop

condition.

FIGURE 3-1: DATA TRANSFER SEQUENCE ON THE SERIAL BUS

Note: The 24XX01 does not generate any

Acknowledge bits if an internal

programming cycle is in progress.

SCL

SDA

(A) (B) (D) (D) (A)(C)

Start

Condition

Address or

Acknowledge

Valid

Data

Allowed

to Change

Stop

Condition

评论收藏

内容反馈

keyrua

2011-12-23

有主要代码，但非完整项目。可做参考
crj123456

2015-05-30

有参考价值
chenwqq

2014-09-05

学习可做参考,还行

日月环水天

粉丝: 1
资源: 4

电子计价秤—PIC单片机汇编源程序

PIC单片机汇编运算子程序

PIC单片机电子表源程序

PIC单片机汇编指令

PIC单片机汇编EVEREDIT配置文件

PIC-TEMP.zip_PIC_PIC 单片机 汇编_PIC.asm_pic_temp

单片机电子计价秤单片机电子计价秤.doc

基于AT89C5 1单片机的电子计价秤的设计与实现

基于AT89C51单片机的电子计价秤的设计与实现

基于单片机的出租车计价器设计(附源程序).doc

PIC单片机驱动TM1616源程序

PIC单片机8位无符号乘法汇编

PIC单片机 AD转换 源程序

单片机与DSP中的Wineows下PIC 8位单片机源程序汇编和固化（七）

PIC单片机8位无符号除法汇编

基于AT89C51单片机的电子计价秤的软硬件设计.doc

佰伦斯电子计价秤标定说明书

一个完整的安普特计价秤程序

以高整合度混合信号单片机实现电子计价秤应用

基于PLC技术的电子计价秤自动检定系统设计与实现.pdf

单片机与DSP中的Windows下PIC 8位单片机源程序汇编和固化（三）

单片机与DSP中的Windows下PIC 8位单片机源程序汇编和固化（二）

PIC单片机AD温度源程序

PIC单片机电子课件

单片机与DSP中的Windows下PIC 8位单片机源程序汇编和固化（四）

基于单片机电子秤计价数码管显示串口通信(proteus仿真+源程序+报告）.rar

基于单片机多功能电子计价秤系统设计

电子-一种电子计价秤

基于stm32的电子秤源代码.zip

电子政务-光能电子计价秤.zip

最新资源

PIC-TEMP.zip_PIC_PIC 单片机汇编_PIC.asm_pic_temp

PIC单片机 AD转换源程序