PCI-TO-PCI BRIDGE ARCHITECTURE SPECIFICATION, REV 1.2
4
3.2.5. Bridge Specific Configuration Registers .................................................. 38
3.2.5.1. Base Address Registers..................................................................... 38
3.2.5.1.1. Memory Base Address Register Format ........................................ 39
3.2.5.1.2. I/O Base Address Register Format ................................................ 40
3.2.5.2. Primary Bus Number Register.......................................................... 41
3.2.5.3. Secondary Bus Number Register...................................................... 41
3.2.5.4. Subordinate Bus Number Register.................................................... 41
3.2.5.5. Secondary Latency Timer Register................................................... 41
3.2.5.6. I/O Base Register and I/O Limit Register......................................... 42
3.2.5.7. Secondary Status Register................................................................. 43
3.2.5.8. Memory Base Register and Memory Limit Register........................ 46
3.2.5.9. Prefetchable Memory Base Register and Prefetchable Memory Limit
Register ........................................................................................................... 46
3.2.5.10. Prefetchable Base Upper 32 Bits and Prefetchable Limit Upper 32
Bits Registers ........................................................................................................ 47
3.2.5.11. I/O Base Upper 16 Bits and I/O Limit Upper 16 Bits Registers....... 48
3.2.5.12. Capabilities Pointer........................................................................... 48
3.2.5.13. Subsystem ID and Subsystem Vendor ID......................................... 48
3.2.5.14. Reserved Registers at 35h, 36h, and 37h .......................................... 49
3.2.5.15. Expansion ROM Base Address Register .......................................... 49
3.2.5.16. Interrupt Line Register...................................................................... 50
3.2.5.17. Interrupt Pin Register........................................................................ 50
3.2.5.18. Bridge Control Register .................................................................... 50
3.2.6. Slot Numbering Capabilities List Item...................................................... 56
3.2.6.1. Slot Numbering Capabilities ID........................................................ 56
3.2.6.2. Pointer to Next ID............................................................................. 56
3.2.6.3. Add-in Card Slot Register................................................................. 56
3.2.6.4. Chassis Number Register.................................................................. 57
4. ADDRESS DECODING .......................................................................................... 59
4.1. ADDRESS RANGES ............................................................................................. 59
4.2. I/O ..................................................................................................................... 59
4.2.1. ISA Mode................................................................................................... 61
4.3. MEMORY MAPPED I/O ....................................................................................... 62
4.4. PREFETCHABLE MEMORY .................................................................................. 63
4.4.1. 64-bit Addressing...................................................................................... 64
4.4.2. 64-bit Address Decoding of Prefetchable Memory................................... 66
4.4.2.1. Below the 4-GB Boundary................................................................ 67
4.4.2.2. Above the 4-GB Boundary ............................................................... 67
4.4.2.3. Across the 4-GB Boundary............................................................... 67
4.5. VGA SUPPORT .................................................................................................. 68
4.5.1. VGA Compatible Addressing .................................................................... 68
4.5.2. VGA Palette Snooping .............................................................................. 69
4.6. SUBTRACTIVE DECODE SUPPORT ....................................................................... 69
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