PCI SPECIFICATIONS
VOLUME 1 4 PCI-SIG
PCI LOCAL BUS SPECIFICATION, REV. 3.0
3.3. B
US
T
RANSACTIONS
........................................................................................... 64
3.3.1. Read Transaction ...................................................................................... 65
3.3.2. Write Transaction...................................................................................... 66
3.3.3. Transaction Termination........................................................................... 67
3.4. A
RBITRATION
..................................................................................................... 87
3.4.1. Arbitration Signaling Protocol.................................................................. 89
3.4.2. Fast Back-to-Back Transactions ............................................................... 91
3.4.3. Arbitration Parking ................................................................................... 94
3.5. L
ATENCY
............................................................................................................ 95
3.5.1. Target Latency........................................................................................... 95
3.5.2. Master Data Latency................................................................................. 98
3.5.3. Memory Write Maximum Completion Time Limit.....................................99
3.5.4. Arbitration Latency ................................................................................. 100
3.6. O
THER
B
US
O
PERATIONS
................................................................................. 110
3.6.1. Device Selection ......................................................................................110
3.6.2. Special Cycle ........................................................................................... 111
3.6.3. IDSEL Stepping....................................................................................... 113
3.6.4. Interrupt Acknowledge ............................................................................114
3.7. E
RROR
F
UNCTIONS
........................................................................................... 115
3.7.1. Parity Generation.................................................................................... 115
3.7.2. Parity Checking....................................................................................... 116
3.7.3. Address Parity Errors ............................................................................. 116
3.7.4. Error Reporting....................................................................................... 117
3.7.5. Delayed Transactions an d Data Parity Errors ....................................... 120
3.7.6. Error Recovery........................................................................................ 121
3.8. 64-B
IT
B
US
E
XTENSION
................................................................................... 123
3.8.1. Determining Bus Width During System Initialization............................. 126
3.9. 64-
BIT
A
DDRESSING
......................................................................................... 127
3.10. S
PECIAL
D
ESIGN
C
ONSIDERATIONS
.............................................................. 130
4. ELECTRICAL SPECIFICATION.......................................................................... 137
4.1. O
VERVIEW
....................................................................................................... 137
4.1.1. Transition Road Map .............................................................................. 137
4.1.2. Dynamic vs. Static Drive Specification ................................................... 138
4.2. C
OMPONENT
S
PECIFICATION
............................................................................ 139
4.2.1. 5V Signaling Environment ...................................................................... 140
4.2.2. 3.3V Signaling Environment ................................................................... 146
4.2.3. Timing Specification................................................................................ 150
4.2.4. Indeterminate Inputs and Metastability .................................................. 155
4.2.5. Vendor Provided Specification................................................................ 156
4.2.6. Pinout Recommendation ......................................................................... 157
