华硕A42图纸 主板型号是K42JV REV 2.0

1. This pin should have an external pull-up of 1K Ohms

to 10K Ohms to a rail of 1.05/1.1V which is ON in S0-S3

2. Connect this pin through a voltage divider circuit;

recommend 4.75K Ohms pull-up to DDR3 Power Rail

(VDDQ) of +V1.5U and a 12K Ohms pull-down to

ground to convert to processor’s VTT level.

- 11 = 1 x 16 PEG (Default)

- 10 = 2 x 8 PEG

after RSTIN# de-assertion.

Unmount if Intel has fixed this issue.

- 1:Normal Operation (Default)

- 0:Lane Numbers Reversed 15 -> 0, 14 -> 1, ...

- 1:Disabled - No Physical Display Port attached to Embedded DisplayPort

- 0:Enabled - An external Display Port device is connected to the Embedded Display Port

Clarksfield (only for early samples pre-ES1) - Connect to GND with 3.01K Ohm/5% resistor

For a common motherboard design (for AUB and CFD),

the pull-down resistor should be used. Does not impact Arrandale functionality.