新唐mcu（N76E003）全套DEMO，可直接运行资源-CSDN文库

共789个文件

lst：180个

obj：165个

m51：42个

超低功耗

N76E003

DEMO

直接KEIL运行

5星 · 超过95%的资源需积分: 48 109 浏览量 2018-11-29 15:58:44 上传评论 6 收藏 5.59MB ZIP 举报

资源推荐

资源详情

资源评论

收起资源包目录

新唐mcu（N76E003）全套DEMO，可直接运行（789个子文件）

UID_check.__b 120B

Version.__i 178B

Common.__i 153B

Delay.__i 150B

xRAM_768byte.__i 140B

xRAM_256.__i 128B

testw77.__i 125B

STARTUP.A51 5KB

ADC 193KB

ADC 162KB

ADC_Simple 241KB

ADC_Simple 161KB

GPIO.uvgui.Administrator 137KB

UART0.uvgui.Administrator 137KB

ADC.uvgui.Administrator 136KB

PWM.uvgui.Administrator 136KB

UART0_mode_3.uvgui.Administrator 136KB

IAP_DATAFLSH.uvgui.Administrator 135KB

ADC_Simple.uvgui.Administrator 134KB

GPIO.uvgui_Chuango0591.bak 139KB

Pin_Int.uvgui_Chuango0591.bak 137KB

GPIO.uvgui_Administrator.bak 137KB

UART0.uvgui_Administrator.bak 137KB

UART0_mode_3.uvgui_Chuango0591.bak 136KB

WDT.uvgui_Chuango0591.bak 136KB

UART0_mode_3.uvgui_Administrator.bak 136KB

ADC.uvgui_Administrator.bak 136KB

WDT.uvgui_Chuango0591.bak 136KB

UART0.uvgui_Chuango0591.bak 135KB

WKT_INT.uvgui_Chuango0591.bak 71KB

PWM.uvgui_Chuango0591.bak 70KB

PWM.uvgui_LCWANG0.bak 70KB

ISP_LD-Program-AP.uvgui_Chuango0591.bak 69KB

ADC_Simple.uvgui_Administrator.bak 69KB

I2C_Master.uvgui_Chuango0591.bak 69KB

Timer3.uvgui_Chuango0591.bak 69KB

GPIO_uvproj.bak 14KB

UART0_mode_3_uvproj.bak 14KB

ADC_Simple_uvproj.bak 14KB

UART0_uvproj.bak 14KB

IAP_DATAFLSH_uvproj.bak 14KB

ADC_uvproj.bak 14KB

PWM_uvproj.bak 14KB

ADC_Simple_uvopt.bak 8KB

PWM_uvopt.bak 8KB

GPIO_uvopt.bak 7KB

UART0_mode_3_uvopt.bak 7KB

IAP_DATAFLSH_uvopt.bak 7KB

ADC_uvopt.bak 6KB

UART0_uvopt.bak 6KB

run.bat 18B

isp_ld.bin 2KB

WDT.bin 242B

Capture.c 15KB

I2C_EEPROM.c 12KB

PWM.C 9KB

PWM.c 8KB

I2C_M.c 8KB

Pin_Int.C 7KB

ISP_LD-AP.c 7KB

GPIO.C 7KB

IAP_DATAFLASH.c 7KB

ADC.C 7KB

ADC.C 5KB

I2C_S.c 5KB

Common.c 4KB

Capture.c 4KB

Timer01_M3.c 4KB

Timer01_M1.c 4KB

Delay.c 4KB

IAP_BYTE.c 4KB

Timer01_M0.c 4KB

Timer01_M2.c 4KB

UART0_mode_3.c 4KB

Fsys_SEL.c 4KB

WDT.c 3KB

UART0.c 3KB

WDT.c 3KB

Timer3.c 2KB

WKT_INT.c 2KB

CLK_OUT.c 2KB

xRAM_768byte.c 1KB

UID_check.C 697B

Capture 196KB

Capture 159KB

WKT_INT.uvgui.Chuango0591 139KB

GPIO.uvgui.Chuango0591 139KB

Pin_Int.uvgui.Chuango0591 137KB

UART0_mode_3.uvgui.Chuango0591 136KB

WDT.uvgui.Chuango0591 136KB

UART0.uvgui.Chuango0591 135KB

Capture.uvgui.Chuango0591 71KB

PWM.uvgui.Chuango0591 70KB

Timer2.uvgui.Chuango0591 70KB

FSYS_SEL.uvgui.Chuango0591 69KB

共 789 条

 2002 Microchip Technology Inc. DS21189F-page 1

24AA64/24LC64

Device Selection Table

Features

• Single supply with operation down to 1.8V

• Low power CMOS technology

- 1 mA active current typical

- 1 µA standby current (max.) (I-temp)

• Organized as 8 blocks of 8K bit (64K bit)

• 2-wire serial interface bus, I

C™ compatible

• Cascadable for up to eight devices

• Schmitt Trigger inputs for noise suppression

• Output slope control to eliminate ground bounce

• 100 kHz (24AA64) and 400 kHz (24LC64) com-

patibility

• Self-timed write cycle (including auto-erase)

• Page-write buffer for up to 32 bytes

• 2 ms typical write cycle time for page-write

• Hardware write protect for entire memory

• Can be operated as a serial ROM

• Factory programming (QTP) available

• ESD protection > 4,000V

• 1,000,000 erase/write cycles

• Data retention > 200 years

• 8-lead PDIP, SOIC, TSSOP, and MSOP package

• Available temperature ranges:

Description

The Microchip Technology Inc. 24AA64/24LC64

(24XX64*) is a 64 Kbit Electrically Erasable PROM.

The device is organized as eight blocks of 1K x 8-bit

memory with a 2-wire serial interface. Low voltage

design permits operation down to 1.8V with standby

and active currents of only 1 µA and 1 mA respectively.

It has been developed for advanced, low power appli-

cations such as personal communications or data

acquisition. The 24XX64 also has a page-write capabil-

ity for up to 32 bytes of data. Functional address lines

allow up to eight devices on the same bus, for up to

512 Kbits address space. The 24XX64 is available in

the standard 8-pin PDIP, surface mount SOIC, TSSOP

and MSOP packages.

Package Types

Block Diagram

Part

Number

VCC

Range

Max Clock

Frequency

Temp

Ranges

24AA64 1.8-5.5 400 kHz

(1)

24LC64 2.5-5.5 400 kHz I, E

Note 1: 100 kHz for V

CC <2.5V

- Industrial (I): -40°C to +85°C

- Automotive (E): -40°C to +125°C

24XX64

Vss

Vcc

SCL

SDA

PDIP/SOIC/TSSOP/MSOP

24XX64X

Vcc

SCL

SDA

Vss

ROTATED TSSOP

(24AA64X/24LC64X)

HV GENERATOR

EEPROM

ARRAY

PAGE LATCHES

YDEC

XDEC

SENSE AMP

R/W CONTROL

I/O

CONTROL

LOGIC

I/O

MEMORY

CONTROL

LOGIC

A0 A1 WPA2

SCL

SDA

VSS

64K I

™

Serial EEPROM

*24XX64 is used in this document as a generic part number for the 24AA64/24LC64 devices.

24AA64/24LC64

DS21189F-page 2  2002 Microchip Technology Inc.

1.0 ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings†

VCC.............................................................................................................................................................................6.5V

All inputs and outputs w.r.t. V

SS ......................................................................................................... -0.3V to VCC +1.0V

Storage temperature ...............................................................................................................................-65°C to +150°C

Ambient temp. with power applied ..........................................................................................................-40°C to +125°C

ESD protection on all pins ......................................................................................................................................................≥ 4kV

1.1 DC Characteristics

† NOTICE: Stresses above those listed under “Maximum ratings” may cause permanent damage to the device.

This is a stress rating only and functional operation of the device at those or any other conditions above those

indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions

for extended periods may affect device reliability.

DC CHARACTERISTICS

CC = +1.8V to +5.5V

Industrial (I): T

AMB = -40°C to +85°C

Automotive (E): T

AMB = -40°C to +125°C

Param.

No.

Sym Characteristic Min Typ Max Units Conditions

D1 V

IH WP, SCL and SDA pins — ————

D2 — High level input voltage 0.7 V

CC ——V—

D3 V

IL Low level input voltage — — 0.3 VCC V—

D4 V

HYS Hysteresis of Schmitt

Trigger inputs

0.05 VCC ——V(Note 1)

D5 V

OL Low level output voltage — — 0.40 V IOL = 3.0 mA, VCC = 2.5V

D6 I

LI Input leakage current ——±10µAVIN =.1V to VCC

D7 ILO Output leakage current ——±10µAVOUT =.1V to VCC

D8 CIN,

OUT

Pin capacitance

(all inputs/outputs)

— — 10 pF VCC = 5.0V (Note 1)

AMB = 25°C, FCLK = 1 MHz

D9 I

CC write Operating current —0.1 3mAVCC = 5.5V, SCL = 400 kHz

D10 I

CC read — 0.05 1 mA —

D11 I

CCS Standby current —

—

.01

—

µA

Industrial

Automotive

SDA = SCL = V

WP = VSS

Note 1: This parameter is periodically sampled and not 100% tested.

2: Typical measurements taken at room temperature.

 2002 Microchip Technology Inc. DS21189F-page 3

24AA64/24LC64

1.2 AC Characteristics

AC CHARACTERISTICS

CC = +1.8V to +5.5V

Industrial (I): T

AMB = -40°C to +85°C

Automotive (E): T

AMB = -40°C to +125°C

Param.

No.

Sym Characteristic Min Max Units Conditions

CLK Clock frequency —

—

400

100

kHz 2.5V ≤ VCC ≤ 5.5V

1.8V ≤ V

CC < 2.5V (24AA64)

THIGH Clock high time 600

4000

—

ns 2.5V ≤ VCC ≤ 5.5V

1.8V ≤ V

CC < 2.5V (24AA64)

LOW Clock low time 1300

4700

—

ns 2.5V ≤ VCC ≤ 5.5V

1.8V ≤ V

CC < 2.5V (24AA64)

R SDA and SCL rise time

(Note 1)

—

300

1000

ns 2.5V ≤ VCC ≤ 5.5V

1.8V ≤ V

CC < 2.5V (24AA64)

F SDA and SCL fall time — 300 ns (Note 1)

HD:STA START condition hold time 600

4000

—

ns 2.5V ≤ VCC ≤ 5.5V

1.8V ≤ V

CC < 2.5V (24AA64)

SU:STA START condition setup time 600

4700

—

ns 2.5V ≤ VCC ≤ 5.5V

1.8V ≤ V

CC < 2.5V (24AA64)

HD:DAT Data input hold time 0 — ns (Note 2)

SU:DAT Data input setup time 100

250

—

ns 2.5V ≤ VCC ≤ 5.5V

1.8V ≤ V

CC < 2.5V (24AA64)

10 T

SU:STO STOP condition setup time 600

4000

—

ns 2.5V ≤ VCC ≤ 5.5V

1.8V ≤ V

CC < 2.5V (24AA64)

11 T

AA Output valid from clock

(Note 2)

—

900

3500

ns 2.5V ≤ VCC ≤ 5.5V

1.8V ≤ V

CC < 2.5V (24AA64)

12 T

BUF Bus free time: Time the bus

must be free before a new

transmission can start

1300

4700

—

ns 2.5V ≤ V

CC ≤ 5.5V

1.8V ≤ V

CC < 2.5V (24AA64)

13 T

OF Output fall time from VIH min-

imum to V

IL maximum

20+0.1C

—

250

ns 2.5V ≤ V

CC ≤ 5.5V

1.8V ≤ V

CC ≤ 2.5V (24AA64)

14 T

SP Input filter spike suppression

(SDA and SCL pins)

—50ns(Notes 1 and 3)

15 T

WC Write cycle time (byte or

page)

—5ms—

16 — Endurance 1M — cycles 25°C, V

CC = 5.0V, Block Mode

(Note 4)

Note 1: Not 100% tested. C

B = total capacitance of one bus line in pF.

2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region

(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.

3: The combined T

SP and VHYS specifications are due to new Schmitt Trigger inputs which provide improved

noise spike suppression. This eliminates the need for a

TI specification for standard operation.

4: This parameter is not tested but ensured by characterization. For endurance estimates in a specific appli-

cation, please consult the Total Endurance Model which can be obtained on Microchip’s website:

www.microchip.com.

24AA64/24LC64

DS21189F-page 4  2002 Microchip Technology Inc.

FIGURE 1-1: BUS TIMING DATA

FIGURE 1-2: BUS TIMING START/STOP

SCL

SDA

OUT

START STOP

SCL

SDA

 2002 Microchip Technology Inc. DS21189F-page 5

24AA64/24LC64

2.0 FUNCTIONAL DESCRIPTION

The 24XX64 supports a bi-directional 2-wire bus and

data transmission protocol. A device that sends data

onto the bus is defined as transmitter, and a device

receiving data as receiver. The bus has to be controlled

by a master device which generates the serial clock

(SCL), controls the bus access and generates the

START and STOP conditions, while the 24XX64 works

as slave. Both master and slave can operate as trans-

mitter or receiver, but the master device determines

which mode is activated.

3.0 BUS CHARACTERISTICS

The following bus protocol has been defined:

• Data transfer may be initiated only when the bus

is not busy.

• During data transfer, the data line must remain

stable whenever the clock line is HIGH. Changes

in the data line while the clock line is HIGH will be

interpreted as a START or STOP condition.

Accordingly, the following bus conditions have been

defined (Figure 3-1).

3.1 Bus not Busy (A)

Both data and clock lines remain HIGH.

3.2 Start Data Transfer (B)

A HIGH to LOW transition of the SDA line while the

clock (SCL) is HIGH determines a START condition. All

commands must be preceded by a START condition.

3.3 Stop Data Transfer (C)

A LOW to HIGH transition of the SDA line while the

clock (SCL) is HIGH determines a STOP condition. All

operations must be ended with a STOP condition.

3.4 Data Valid (D)

The state of the data line represents valid data when,

after a START condition, the data line is stable for the

duration of the HIGH period of the clock signal.

The data on the line must be changed during the LOW

period of the clock signal. There is one clock pulse per

bit of data.

Each data transfer is initiated with a START condition

and terminated with a STOP condition. The number of

the data bytes transferred between the START and

STOP conditions is determined by the master device

and is theoretically unlimited, although only the last six-

teen will be stored when doing a write operation. When

an overwrite does occur it will replace data in a first-in

first-out (FIFO) fashion.

3.5 Acknowledge

Each receiving device, when addressed, is obliged to

generate an acknowledge after the reception of each

byte. The master device must generate an extra clock

pulse which is associated with this Acknowledge bit.

The device that acknowledges, has to pull down the

SDA line during the acknowledge clock pulse in such a

way that the SDA line is stable LOW during the HIGH

period of the acknowledge related clock pulse. Of

course, setup and hold times must be taken into

account. During reads, a master must signal an end of

data to the slave by not generating an Acknowledge bit

on the last byte that has been clocked out of the slave.

In this case, the slave (24XX64) will leave the data line

HIGH to enable the master to generate the STOP con-

dition.

FIGURE 3-1: DATA TRANSFER SEQUENCE ON THE SERIAL BUS

Note: The 24XX64 does not generate any

Acknowledge bits if an internal program-

ming cycle is in progress.

SCL

SDA

(A) (B) (D) (D) (A)(C)

START

CONDITION

ADDRESS OR

ACKNOWLEDGE

VALID

DATA

ALLOWED

TO CHANGE

STOP

CONDITION

评论收藏

内容反馈

骏晔科技IOT

2020-07-03

原原本本github上面的
leewen420

2018-12-11

不错，可以使用，很好。

创高陈

粉丝: 3
资源: 6

新唐mcu（N76E003）全套DEMO，可直接运行

新唐N76E003开发全套资料

N76E003的多路ADC示例(可直接编译使用的完整例子)

新唐CPU芯片的一个例程

N76E003 程序框架 例程.rar

N76E003 Demo_v1_新唐单片机测试激光模块_N76E003IIC_n76e003iic_新唐_N76E003AT20

新唐N76E003AT20例程BSP资料.zip

新塘N76E003开发官方例程

新唐全系列单片机烧录软件.zip

新唐MCU烧录工具 2.0

N76E003开发资料

新唐N76E003资料以及库文件

国产新塘单片机-N76E003开发资料（参考手册+keil代码+芯片硬件原理图）

N76E003单片机IO口中断示例代码

新唐 N76E003 中文手册 保证是中文的

N76E003参考代码

N76E003资料N76E003资料

N76E003_BSP_Keil_C51源码例程

nuvoton N76E003 BSP Keil_C51

N76E003呼吸灯程序（PWM中断&重设占空比）

新唐单片机N76E003AD原理图和封装

N76E003单片机PWM程序（边沿对齐，独立输出模式）

4路PWM脉冲捕捉

2019新唐MCU选型表.pdf

新塘 单片机例程 库函数操作

新唐单片机I91200程序demo

N76E003单片机串口BUG修改

新唐N76E003部分例程

新唐N76E003单片机参考设计原理图+实验例程源码合集（38例）.zip

N76E003新唐无线充电方案原理图pcb文件源码全部制作资料.rar

最新资源

N76E003 程序框架例程.rar

新唐 N76E003 中文手册保证是中文的

新塘单片机例程库函数操作