MSP432E4 SimpleLink™ Microcontrollers
Technical Reference Manual
Literature Number: SLAU723A
October 2017–Revised October 2018
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SLAU723A–October 2017–Revised October 2018
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Copyright © 2017–2018, Texas Instruments Incorporated
Contents
Contents
Preface....................................................................................................................................... 77
1 Cortex
®
-M4F Processor ....................................................................................................... 79
1.1 Introduction.................................................................................................................. 80
1.2 Block Diagram .............................................................................................................. 81
1.3 Overview..................................................................................................................... 82
1.3.1 System-Level Interface ........................................................................................... 82
1.3.2 Integrated Configurable Debug.................................................................................. 82
1.3.3 Trace Port Interface Unit (TPIU) ................................................................................ 82
1.3.4 Cortex-M4F System Component Details ....................................................................... 83
1.4 Programming Model ....................................................................................................... 83
1.4.1 Processor Mode and Privilege Levels for Software Execution .............................................. 83
1.4.2 Stacks............................................................................................................... 84
1.4.3 Exceptions and Interrupts ........................................................................................ 97
1.4.4 Data Types......................................................................................................... 97
1.5 Memory Model.............................................................................................................. 97
1.5.1 Memory Regions, Types, and Attributes...................................................................... 100
1.5.2 Memory System Ordering of Memory Accesses ............................................................ 100
1.5.3 Behavior of Memory Accesses................................................................................. 100
1.5.4 Software Ordering of Memory Accesses ..................................................................... 101
1.5.5 Bit-Banding ....................................................................................................... 102
1.5.6 Data Storage ..................................................................................................... 104
1.5.7 Synchronization Primitives...................................................................................... 104
1.6 Exception Model .......................................................................................................... 105
1.6.1 Exception States ................................................................................................. 106
1.6.2 Exception Types ................................................................................................. 106
1.6.3 Exception Handlers.............................................................................................. 108
1.6.4 Vector Table...................................................................................................... 108
1.6.5 Exception Priorities .............................................................................................. 109
1.6.6 Interrupt Priority Grouping ...................................................................................... 110
1.6.7 Exception Entry and Return .................................................................................... 110
1.7 Fault Handling............................................................................................................. 113
1.7.1 Fault Types ....................................................................................................... 113
1.7.2 Fault Escalation and Hard Faults.............................................................................. 113
1.7.3 Fault Status Registers and Fault Address Registers........................................................ 114
1.7.4 Lockup............................................................................................................. 114
1.8 Power Management ...................................................................................................... 114
1.8.1 Entering Sleep Modes........................................................................................... 115
1.8.2 Wake Up From Sleep Mode.................................................................................... 115
1.9 Instruction Set Summary................................................................................................. 115
2 Cortex-M4 Peripherals....................................................................................................... 121
2.1 Introduction ................................................................................................................ 122
2.2 Functional Description.................................................................................................... 122
2.2.1 System Timer (SysTick)......................................................................................... 122
2.2.2 Nested Vectored Interrupt Controller (NVIC)................................................................. 123
2.2.3 System Control Block (SCB) ................................................................................... 124
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2.2.4 Memory Protection Unit (MPU) ................................................................................ 124
2.2.5 Floating-Point Unit (FPU) ....................................................................................... 128
2.3 SysTick Registers......................................................................................................... 133
2.3.1 STCTRL Register (Offset = 0x10) [reset = 0x0] ............................................................. 134
2.3.2 STRELOAD Register (Offset = 0x14) [reset = 0x0] ......................................................... 135
2.3.3 STCURRENT Register (Offset = 0x18) [reset = 0x0] ....................................................... 136
2.4 NVIC Registers............................................................................................................ 137
2.4.1 EN0 to EN3 Registers........................................................................................... 139
2.4.2 DIS0 to DIS3 Registers ......................................................................................... 140
2.4.3 PEND0 to PEND 3 Registers .................................................................................. 141
2.4.4 UNPEND0 to UNPEND3 Registers ........................................................................... 142
2.4.5 ACTIVE0 to ACTIVE3 Registers............................................................................... 143
2.4.6 PRI0 to PRI28 Registers........................................................................................ 144
2.4.7 SWTRIG Register (Offset = 0xF00) [reset = 0x0] ........................................................... 146
2.5 SCB Registers............................................................................................................. 147
2.5.1 ACTLR Register (Offset = 0x8) [reset = 0x0] ................................................................ 148
2.5.2 CPUID Register (Offset = 0xD00) [reset = 0x410FC241] .................................................. 149
2.5.3 INTCTRL Register (Offset = 0xD04) [reset = 0x0] .......................................................... 150
2.5.4 VTABLE Register (Offset = 0xD08) [reset = 0x0] ........................................................... 152
2.5.5 APINT Register (Offset = 0xD0C) [reset = 0xFA050000] .................................................. 153
2.5.6 SYSCTRL Register (Offset = 0xD10) [reset = 0x0] ......................................................... 155
2.5.7 CFGCTRL Register (Offset = 0xD14) [reset = 0x200] ...................................................... 156
2.5.8 SYSPRI1 Register (Offset = 0xD18) [reset = 0x0] .......................................................... 157
2.5.9 SYSPRI2 Register (Offset = 0xD1C) [reset = 0x0] .......................................................... 158
2.5.10 SYSPRI3 Register (Offset = 0xD20) [reset = 0x0] ......................................................... 159
2.5.11 SYSHNDCTRL Register (Offset = 0xD24) [reset = 0x0] .................................................. 160
2.5.12 FAULTSTAT Register (Offset = 0xD28) [reset = 0x0] ..................................................... 162
2.5.13 HFAULTSTAT Register (Offset = 0xD2C) [reset = 0x0]................................................... 165
2.5.14 MMADDR Register (Offset = 0xD34) [reset = X] ........................................................... 166
2.5.15 FAULTADDR Register (Offset = 0xD38) [reset = X] ....................................................... 167
2.6 MPU Registers ............................................................................................................ 168
2.6.1 MPUTYPE Register (Offset = 0xD90) [reset = 0x800]...................................................... 169
2.6.2 MPUCTRL Register (Offset = 0xD94) [reset = 0x0]......................................................... 170
2.6.3 MPUNUMBER Register (Offset = 0xD98) [reset = 0x0] .................................................... 172
2.6.4 MPUBASEn Registers .......................................................................................... 173
2.6.5 MPUATTRn Registers........................................................................................... 175
2.7 FPU Registers............................................................................................................. 177
2.7.1 CPAC Register (Offset = 0xD88) [reset = 0x0] .............................................................. 178
2.7.2 FPCC Register (Offset = 0xF34) [reset = 0xC0000000].................................................... 179
2.7.3 FPCA Register (Offset = 0xF38) [reset = X] ................................................................. 181
2.7.4 FPDSC Register (Offset = 0xF3C) [reset = X] ............................................................... 182
3 JTAG Interface ................................................................................................................. 183
3.1 Introduction ................................................................................................................ 184
3.2 Block Diagram............................................................................................................. 184
3.3 Functional Description.................................................................................................... 185
3.3.1 JTAG Interface Pins ............................................................................................. 185
3.3.2 JTAG TAP Controller............................................................................................ 187
3.3.3 Shift Registers.................................................................................................... 187
3.3.4 Operational Considerations..................................................................................... 187
3.4 Initialization and Configuration .......................................................................................... 190
3.5 Register Descriptions..................................................................................................... 190
3.5.1 Instruction Register (IR)......................................................................................... 190
3.5.2 Data Registers ................................................................................................... 192
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Contents
4 System Control................................................................................................................. 194
4.1 Functional Description.................................................................................................... 195
4.1.1 Device Identification ............................................................................................. 195
4.1.2 Reset Control..................................................................................................... 195
4.1.3 Nonmaskable Interrupt .......................................................................................... 201
4.1.4 Power Control .................................................................................................... 202
4.1.5 Clock Control ..................................................................................................... 203
4.1.6 System Control................................................................................................... 210
4.2 System Control Registers................................................................................................ 217
4.2.1 DID0 Register (Offset = 0x0) [reset = X]...................................................................... 222
4.2.2 DID1 Register (Offset = 0x4) [reset = X]...................................................................... 224
4.2.3 PTBOCTL Register (Offset = 0x38) [reset = 0x3] ........................................................... 226
4.2.4 RIS Register (Offset = 0x50) [reset = 0x0] ................................................................... 227
4.2.5 IMC Register (Offset = 0x54) [reset = 0x0]................................................................... 229
4.2.6 MISC Register (Offset = 0x58) [reset = 0x0] ................................................................. 230
4.2.7 RESC Register (Offset = 0x5C) [reset = X] .................................................................. 232
4.2.8 PWRTC Register (Offset = 0x60) [reset = 0x0].............................................................. 234
4.2.9 NMIC Register (Offset = 0x64) [reset = 0x0]................................................................. 235
4.2.10 MOSCCTL Register (Offset = 0x7C) [reset = 0xC]......................................................... 237
4.2.11 RSCLKCFG Register (Offset = 0xB0) [reset = 0x0]........................................................ 239
4.2.12 MEMTIM0 Register (Offset = 0xC0) [reset = 0x00200030] ............................................... 241
4.2.13 ALTCLKCFG Register (Offset = 0x138) [reset = 0x0] ..................................................... 244
4.2.14 DSCLKCFG Register (Offset = 0x144) [reset = 0x0] ...................................................... 245
4.2.15 DIVSCLK Register (Offset = 0x148) [reset = 0x0].......................................................... 247
4.2.16 SYSPROP Register (Offset = 0x14C) [reset = 0x00031F31] ............................................. 248
4.2.17 PIOSCCAL Register (Offset = 0x150) [reset = 0x0] ....................................................... 250
4.2.18 PIOSCSTAT Register (Offset = 0x154) [reset = 0x00400040] ........................................... 251
4.2.19 PLLFREQ0 Register (Offset = 0x160) [reset = 0x0] ....................................................... 252
4.2.20 PLLFREQ1 Register (Offset = 0x164) [reset = 0x0] ....................................................... 253
4.2.21 PLLSTAT Register (Offset = 0x168) [reset = 0x0] ......................................................... 254
4.2.22 SLPPWRCFG Register (Offset = 0x188) [reset = 0x0] .................................................... 255
4.2.23 DSLPPWRCFG Register (Offset = 0x18C) [reset = 0x0].................................................. 256
4.2.24 NVMSTAT Register (Offset = 0x1A0) [reset = 0x1] ........................................................ 258
4.2.25 LDOSPCTL Register (Offset = 0x1B4) [reset = 0x18] ..................................................... 259
4.2.26 LDOSPCAL Register (Offset = 0x1B8) [reset = 0x1818] .................................................. 260
4.2.27 LDODPCTL Register (Offset = 0x1BC) [reset = 0x12]..................................................... 261
4.2.28 LDODPCAL Register (Offset = 0x1C0) [reset = 0x1212].................................................. 262
4.2.29 SDPMST Register (Offset = 0x1CC) [reset = 0x0] ......................................................... 263
4.2.30 RESBEHAVCTL Register (Offset = 0x1D8) [reset = 0x00FFFFFF]...................................... 265
4.2.31 HSSR Register (Offset = 0x1F4) [reset = 0x0] ............................................................. 266
4.2.32 USBPDS Register (Offset = 0x280) [reset = 0x3F] ........................................................ 267
4.2.33 USBMPC Register (Offset = 0x284) [reset = 0x3].......................................................... 268
4.2.34 EMACPDS Register (Offset = 0x288) [reset = 0x3F] ...................................................... 269
4.2.35 EMACMPC Register (Offset = 0x28C) [reset = 0x3] ....................................................... 270
4.2.36 LCDPDS Register (Offset = 0x290) [reset = 0x3F]......................................................... 271
4.2.37 LCDMPC Register (Offset = 0x294) [reset = 0x3].......................................................... 272
4.2.38 CAN0PDS Register (Offset = 0x298) [reset = 0x3F]....................................................... 273
4.2.39 CAN0MPC Register (Offset = 0x29C) [reset = 0x3]........................................................ 274
4.2.40 CAN1PDS Register (Offset = 0x2A0) [reset = 0x3F] ...................................................... 275
4.2.41 CAN1MPC Register (Offset = 0x2A4) [reset = 0x3]........................................................ 276
4.2.42 PPWD Register (Offset = 0x300) [reset = 0x3] ............................................................. 277
4.2.43 PPTIMER Register (Offset = 0x304) [reset = 0xFF] ....................................................... 278
4.2.44 PPGPIO Register (Offset = 0x308) [reset = 0x3FFFF] .................................................... 279
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4.2.45 PPDMA Register (Offset = 0x30C) [reset = 0x1] ........................................................... 281
4.2.46 PPEPI Register (Offset = 0x310) [reset = 0x1] ............................................................. 282
4.2.47 PPHIB Register (Offset = 0x314) [reset = 0x01]............................................................ 283
4.2.48 PPUART Register (Offset = 0x318) [reset = 0xFF] ........................................................ 284
4.2.49 PPSSI Register (Offset = 0x31C) [reset = 0xF]............................................................. 285
4.2.50 PPI2C Register (Offset = 0x320) [reset = 0x3FF] .......................................................... 286
4.2.51 PPUSB Register (Offset = 0x328) [reset = 0x1] ............................................................ 287
4.2.52 PPEPHY Register (Offset = 0x330) [reset = 0x1] .......................................................... 288
4.2.53 PPCAN Register (Offset = 0x334) [reset = 0x3]............................................................ 289
4.2.54 PPADC Register (Offset = 0x338) [reset = 0x3]............................................................ 290
4.2.55 PPACMP Register (Offset = 0x33C) [reset = 0x1] ......................................................... 291
4.2.56 PPPWM Register (Offset = 0x340) [reset = 0x1] ........................................................... 292
4.2.57 PPQEI Register (Offset = 0x344) [reset = 0x1] ............................................................. 293
4.2.58 PPEEPROM Register (Offset = 0x358) [reset = 0x01] .................................................... 294
4.2.59 PPCCM Register (Offset = 0x374) [reset = 0x01] .......................................................... 295
4.2.60 PPLCD Register (Offset = 0x390) [reset = 0x01]........................................................... 296
4.2.61 PPOWIRE Register (Offset = 0x398) [reset = 0x01] ....................................................... 297
4.2.62 PPEMAC Register (Offset = 0x39C) [reset = 0x01]........................................................ 298
4.2.63 PPPRB Register (Offset = 0x3A0) [reset = 0x00] .......................................................... 299
4.2.64 SRWD Register (Offset = 0x500) [reset = 0x00] ........................................................... 300
4.2.65 SRTIMER Register (Offset = 0x504) [reset = 0x00]........................................................ 301
4.2.66 SRGPIO Register (Offset = 0x508) [reset = 0x00] ......................................................... 302
4.2.67 SRDMA Register (Offset = 0x50C) [reset = 0x00] ......................................................... 304
4.2.68 SREPI Register (Offset = 0x510) [reset = 0x00]............................................................ 305
4.2.69 SRHIB Register (Offset = 0x514) [reset = 0x00] ........................................................... 306
4.2.70 SRUART Register (Offset = 0x518) [reset = 0x00]......................................................... 307
4.2.71 SRSSI Register (Offset = 0x51C) [reset = 0x0]............................................................. 309
4.2.72 SRI2C Register (Offset = 0x520) [reset = 0x0] ............................................................. 310
4.2.73 SRUSB Register (Offset = 0x528) [reset = 0x0]............................................................ 312
4.2.74 SREPHY Register (Offset = 0x530) [reset = 0x0] .......................................................... 313
4.2.75 SRCAN Register (Offset = 0x534) [reset = 0x0]............................................................ 314
4.2.76 SRADC Register (Offset = 0x538) [reset = 0x0]............................................................ 315
4.2.77 SRACMP Register (Offset = 0x53C) [reset = 0x0] ......................................................... 316
4.2.78 SRPWM Register (Offset = 0x540) [reset = 0x0]........................................................... 317
4.2.79 SRQEI Register (Offset = 0x544) [reset = 0x0]............................................................. 318
4.2.80 SREEPROM Register (Offset = 0x558) [reset = 0x0]...................................................... 319
4.2.81 SRCCM Register (Offset = 0x574) [reset = 0x0] ........................................................... 320
4.2.82 SRLCD Register (Offset = 0x590) [reset = 0x0] ............................................................ 321
4.2.83 SROWIRE Register (Offset = 0x598) [reset = 0x0] ........................................................ 322
4.2.84 SREMAC Register (Offset = 0x59C) [reset = 0x0] ......................................................... 323
4.2.85 RCGCWD Register (Offset = 0x600) [reset = 0x0]......................................................... 324
4.2.86 RCGCTIMER Register (Offset = 0x604) [reset = 0x00] ................................................... 325
4.2.87 RCGCGPIO Register (Offset = 0x608) [reset = 0x00] ..................................................... 326
4.2.88 RCGCDMA Register (Offset = 0x60C) [reset = 0x0]....................................................... 328
4.2.89 RCGCEPI Register (Offset = 0x610) [reset = 0x0]......................................................... 329
4.2.90 RCGCHIB Register (Offset = 0x614) [reset = 0x1]......................................................... 330
4.2.91 RCGCUART Register (Offset = 0x618) [reset = 0x00] .................................................... 331
4.2.92 RCGCSSI Register (Offset = 0x61C) [reset = 0x0] ........................................................ 332
4.2.93 RCGCI2C Register (Offset = 0x620) [reset = 0x00]........................................................ 333
4.2.94 RCGCUSB Register (Offset = 0x628) [reset = 0x0]........................................................ 335
4.2.95 RCGCEPHY Register (Offset = 0x630) [reset = 0x0]...................................................... 336
4.2.96 RCGCCAN Register (Offset = 0x634) [reset = 0x0]........................................................ 337
4.2.97 RCGCADC Register (Offset = 0x638) [reset = 0x0]........................................................ 338
