+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Legal Partition Candidates ;
+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;
+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
; h ; 8 ; 0 ; 1 ; 0 ; 7 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; m ; 8 ; 0 ; 0 ; 0 ; 7 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; s ; 8 ; 0 ; 0 ; 0 ; 7 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; clkkk ; 2 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
基于verilog实现12/24 小时计时与报时等功能的时钟
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2020-02-16
22:15:10
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基于verilog实现12/24 小时计时与报时等功能的时钟 （419个子文件） 
_info 3KB _info 2KB _vmake 26B _vmake 26B test3.root_partition.cmp.ammdb 748B test3.vpr.ammdb 551B wml3902_digtalclock.vpr.ammdb 412B wml3902_digtalclock.root_partition.cmp.ammdb 397B wml3902_digtalclock.map.ammdb 129B test3.map.ammdb 129B wml3902_timer24_12.vt.bak 3KB timer24_12.vt.bak 3KB wml3902_ledon.vt.bak 3KB hour.vt.bak 3KB minute.vt.bak 3KB wml3902_audio.vt.bak 3KB second.vt.bak 3KB wml3902_clk50mto5hz.vt.bak 3KB clk50mto1hz.vt.bak 3KB wml3902_ledon.v.bak 2KB wml3902_digtalclock_run_msim_rtl_verilog.do.bak 1KB wml3902_hour.v.bak 1KB hour.v.bak 881B wml3902_timer24_12.v.bak 557B test3_run_msim_rtl_verilog.do.bak 541B timer24_12.v.bak 482B wml3902_minute.v.bak 470B minute.v.bak 418B wml3902_second.v.bak 390B wml3902_clk50mto1hz.v.bak 341B wml3902_clk50mto5hz.v.bak 339B clk50mto1hz.v.bak 258B wml3902_audio.v.bak 225B second.v.bak 200B wml3902_digtalclock_run_msim_rtl_verilog.do.bak1 1KB test3_run_msim_rtl_verilog.do.bak1 541B wml3902_digtalclock_run_msim_rtl_verilog.do.bak10 1KB test3_run_msim_rtl_verilog.do.bak10 579B test3_run_msim_rtl_verilog.do.bak11 936B wml3902_digtalclock_run_msim_rtl_verilog.do.bak11 814B wml3902_digtalclock_run_msim_rtl_verilog.do.bak2 1KB test3_run_msim_rtl_verilog.do.bak2 936B wml3902_digtalclock_run_msim_rtl_verilog.do.bak3 1KB test3_run_msim_rtl_verilog.do.bak3 600B wml3902_digtalclock_run_msim_rtl_verilog.do.bak4 1KB test3_run_msim_rtl_verilog.do.bak4 585B wml3902_digtalclock_run_msim_rtl_verilog.do.bak5 1KB test3_run_msim_rtl_verilog.do.bak5 585B wml3902_digtalclock_run_msim_rtl_verilog.do.bak6 1KB test3_run_msim_rtl_verilog.do.bak6 579B wml3902_digtalclock_run_msim_rtl_verilog.do.bak7 1KB test3_run_msim_rtl_verilog.do.bak7 579B wml3902_digtalclock_run_msim_rtl_verilog.do.bak8 1KB test3_run_msim_rtl_verilog.do.bak8 579B wml3902_digtalclock_run_msim_rtl_verilog.do.bak9 1KB test3_run_msim_rtl_verilog.do.bak9 579B test1.bdf 14KB test3.cmp.bpm 1006B test3.map.bpm 974B wml3902_digtalclock.ace_cmp.bpm 867B wml3902_digtalclock.cmp.bpm 760B wml3902_digtalclock.map.bpm 722B wml3902_timer24_12.bsf 3KB wml3902_ledon.bsf 3KB wml3902_hour.bsf 3KB wml3902_audio.bsf 2KB wml3902_digtalclock.ace_cmp.cdb 66KB test3.cmp.cdb 36KB test3.root_partition.cmp.cdb 15KB wml3902_digtalclock.cmp.cdb 12KB test3.map.cdb 12KB test3.root_partition.map.cdb 11KB wml3902_digtalclock.(21).cnf.cdb 10KB test3.rtlv_sg.cdb 10KB test3.sgdiff.cdb 9KB wml3902_digtalclock.(18).cnf.cdb 7KB wml3902_digtalclock.root_partition.cmp.cdb 6KB wml3902_digtalclock.(10).cnf.cdb 6KB wml3902_digtalclock.(4).cnf.cdb 6KB wml3902_digtalclock.rtlv_sg.cdb 5KB test3.(0).cnf.cdb 5KB wml3902_digtalclock.map.cdb 5KB wml3902_digtalclock.root_partition.map.cdb 5KB wml3902_digtalclock.sgdiff.cdb 5KB wml3902_digtalclock.(22).cnf.cdb 4KB wml3902_digtalclock.(3).cnf.cdb 3KB test3.(1).cnf.cdb 3KB wml3902_digtalclock.(5).cnf.cdb 3KB wml3902_digtalclock.(6).cnf.cdb 2KB wml3902_digtalclock.(0).cnf.cdb 2KB test3.(2).cnf.cdb 2KB wml3902_digtalclock.(1).cnf.cdb 2KB test3.map_bb.cdb 2KB wml3902_digtalclock.(2).cnf.cdb 2KB test3.(4).cnf.cdb 2KB test3.(3).cnf.cdb 2KB wml3902_digtalclock.map_bb.cdb 2KB wml3902_digtalclock.(23).cnf.cdb 2KB test3.root_partition.map.hbdb.cdb 1KB wml3902_digtalclock.root_partition.map.hbdb.cdb 1KB共 419 条
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