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All rights reserved.
Reproduction in whole or in part is prohibited without the prior written permission of the copyright holder.
March 2009
nRF24LE1
Ultra-low Power Wireless System On-Chip
Solution
Product Specification v1.2
Key Features
• nRF24L01+ 2.4GHz transceiver (250 kbps,
1 Mbps and 2 Mbps air data rates)
• Fast microcontroller (8051 compatible)
• 16 kB program memory (on-chip Flash)
• 1 kB data memory (on-chip RAM)
• 1 kB NV data memory
• 512 bytes NV data memory (extended endur-
ance)
• AES encryption HW accelerator
• 16-32bit multiplication/division co-processor
(MDU)
• 6-12 bit ADC
• High flexibility IOs
• Serves a set of power modes from ultra low
power to a power efficient active mode
• Several versions in various QFN packages:
X 4x4mm QFN24
X 5x5mm QFN32
X 7x7mm QFN48
• Support for HW debugger
• HW support for firmware upgrade
Applications
• PC peripherals
X Mouse
X Keyboard
X Remote control
X Gaming
• Advanced remote controls
X Audio/Video
X Entertainment centers
X Home appliances
• Goods tracking and monitoring:
X Active RFID
X Sensor networks
• Security systems
X Payment
X Alarm
X Access control
• Health, wellness and sports
X Watches
X Mini computers
X Sensors
• Remote control toys
Revision 1.2 2 of 195
nRF24LE1 Product Specification
Liability disclaimer
Nordic Semiconductor ASA reserves the right to make changes without further notice to the product to
improve reliability, function or design. Nordic Semiconductor ASA does not assume any liability arising out
of the application or use of any product or circuits described herein.
All application information is advisory and does not form part of the specification.
Limiting values
Stress above one or more of the limiting values may cause permanent damage to the device. These are
stress ratings only and operation of the device at these or at any other conditions above those given in the
specifications are not implied. Exposure to limiting values for extended periods may affect device reliability.
Life support applications
These products are not designed for use in life support appliances, devices, or systems where malfunction
of these products can reasonably be expected to result in personal injury. Nordic Semiconductor ASA cus-
tomers using or selling these products for use in such applications do so at their own risk and agree to fully
indemnify Nordic Semiconductor ASA for any damages resulting from such improper use or sale.
Contact details
For your nearest dealer, please see www.nordicsemi.no
Main office:
Otto Nielsens vei 12
7004 Trondheim
Norway
Phone: +47 72 89 89 00
Fax: +47 72 89 89 89
ww.nordicsemi.no
Data sheet status
Objective product specification This product specification contains target specifications for product
development.
Preliminary product specification This product specification contains preliminary data; supplementary
data may be published from Nordic Semiconductor ASA later.
Product specification This product specification contains final product specifications. Nordic
Semiconductor ASA reserves the right to make changes at any time
without notice in order to improve design and supply the best possible
product.
Revision 1.2 3 of 195
nRF24LE1 Product Specification
Revision History
Date Version Description
March 2009 1.2 Updated Figure 33.
and Figure
34. and Table 35. on page 79.
Attention!
Observe precaution for handling
Electrostatic Sensitive Device.
HBM (Human Body Model): Class 1B
CDM (Charged Device Model): Class IV
Revision 1.2 4 of 195
nRF24LE1 Product Specification
Contents
1 Introduction ............................................................................................... 10
1.1 Prerequisites ........................................................................................ 10
1.2 Writing conventions.............................................................................. 10
2 Product overview ...................................................................................... 11
2.1 Features ............................................................................................... 11
2.2 Block diagram ...................................................................................... 13
2.3 Pin assignments................................................................................... 14
2.3.1 24-pin 4x4 QFN-package variant..................................................... 14
2.3.2 32-pin 5x5 QFN-package variant..................................................... 14
2.3.3 48-pin 7x7 QFN-package variant..................................................... 15
2.4 Pin functions......................................................................................... 15
3 RF Transceiver .......................................................................................... 16
3.1 Features ............................................................................................... 16
3.2 Block diagram ...................................................................................... 17
3.3 Functional description .......................................................................... 17
3.3.1 Operational Modes .......................................................................... 17
3.3.2 Air data rate ..................................................................................... 21
3.3.3 RF channel frequency ..................................................................... 21
3.3.4 Received Power Detector measurements ....................................... 21
3.3.5 PA control ........................................................................................ 21
3.3.6 RX/TX control .................................................................................. 22
3.4 Enhanced ShockBurst™ ...................................................................... 22
3.4.1 Features .......................................................................................... 22
3.4.2 Enhanced ShockBurst™ overview .................................................. 22
3.4.3 Enhanced Shockburst™ packet format ........................................... 23
3.4.4 Automatic packet assembly............................................................. 26
3.4.5 Automatic packet disassembly ........................................................ 27
3.4.6 Automatic packet transaction handling............................................ 28
3.4.7 Enhanced ShockBurst flowcharts.................................................... 30
3.4.8 MultiCeiver™ ................................................................................... 33
3.4.9 Enhanced ShockBurst™ timing....................................................... 35
3.4.10 Enhanced ShockBurst™ transaction diagram................................. 38
3.4.11 Compatibility with ShockBurst™...................................................... 42
3.5 Data and control interface .................................................................... 43
3.5.1 SFR registers................................................................................... 43
3.5.2 SPI operation................................................................................... 44
3.5.3 Data FIFO........................................................................................ 46
3.5.4 Interrupt ........................................................................................... 47
3.6 Register map........................................................................................ 48
3.6.1 Register map table .......................................................................... 48
4 MCU ............................................................................................................ 54
4.1 Block diagram ...................................................................................... 55
4.2 Features ............................................................................................... 55
4.3 Functional description .......................................................................... 56
Revision 1.2 5 of 195
nRF24LE1 Product Specification
4.3.1 Arithmetic Logic Unit (ALU) ............................................................. 56
4.3.2 Instruction set summary .................................................................. 56
4.3.3 Opcode map .................................................................................... 60
5 Memory and I/O organization................................................................... 62
5.1 PDATA memory addressing................................................................. 63
5.2 MCU Special Function Registers ......................................................... 63
5.2.1 Accumulator - ACC.......................................................................... 63
5.2.2 B Register – B ................................................................................. 63
5.2.3 Program Status Word Register - PSW ............................................ 64
5.2.4 Stack Pointer – SP .......................................................................... 64
5.2.5 Data Pointer – DPH, DPL ................................................................ 64
5.2.6 Data Pointer 1 – DPH1, DPL1 ......................................................... 65
5.2.7 Data Pointer Select Register – DPS................................................ 65
5.2.8 PCON register ................................................................................. 65
5.2.9 Special Function Register Map........................................................ 66
5.2.10 Special Function Registers reset values ......................................... 67
6 Flash memory............................................................................................ 70
6.1 Features ............................................................................................... 70
6.2 Block diagram ...................................................................................... 70
6.3 Functional description .......................................................................... 71
6.3.1 Using the NV data memory ............................................................. 71
6.3.2 Flash memory configuration ............................................................ 71
6.3.3 Brown-out ........................................................................................ 76
6.3.4 Flash programming from the MCU .................................................. 77
6.3.5 Flash programming through SPI...................................................... 77
6.3.6 Hardware support for firmware upgrade.......................................... 81
7 Random Access memory (RAM).............................................................. 84
7.1 SRAM configuration ............................................................................. 84
8 Timers/counters ........................................................................................ 86
8.1 Features ............................................................................................... 86
8.2 Block diagram ...................................................................................... 86
8.3 Functional description .......................................................................... 87
8.3.1 Timer 0 and Timer 1 ........................................................................ 87
8.3.2 Timer 2 ............................................................................................ 89
8.4 SFR registers ....................................................................................... 91
8.4.1 Timer/Counter control register – TCON........................................... 91
8.4.2 Timer mode register - TMOD........................................................... 92
8.4.3 Timer 0 – TH0, TL0 ......................................................................... 92
8.4.4 Timer 1 – TH1, TL1 ......................................................................... 92
8.4.5 Timer 2 control register – T2CON ................................................... 93
8.4.6 Timer 2 – TH2, TL2 ......................................................................... 93
8.4.7 Compare/Capture enable register – CCEN ..................................... 94
8.4.8 Capture registers – CC1, CC2, CC3 ............................................... 94
8.4.9 Compare/Reload/Capture register – CRCH, CRCL ........................ 95
8.5 Real Time Clock - RTC ........................................................................ 95
8.5.1 Features .......................................................................................... 95
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