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6.2 Architecture ................................................................................................................. 99
6.2.1 Privilege Levels ................................................................................................... 99
6.2.2 Memory Protection Ranges .................................................................................... 100
6.2.3 Permission Structures .......................................................................................... 100
6.2.4 Protection Check ................................................................................................ 101
6.2.5 DSP L1/L2 Cache Controller Accesses ...................................................................... 102
6.2.6 MPU Register Protection ....................................................................................... 102
6.2.7 Invalid Accesses and Exceptions ............................................................................. 102
6.2.8 Reset Considerations ........................................................................................... 102
6.2.9 Interrupt Support ................................................................................................ 103
6.2.10 Emulation Considerations ..................................................................................... 103
6.3 MPU Registers ........................................................................................................... 104
6.3.1 Revision Identification Register (REVID) .................................................................... 106
6.3.2 Configuration Register (CONFIG) ............................................................................ 106
6.3.3 Interrupt Raw Status/Set Register (IRAWSTAT) ............................................................ 107
6.3.4 Interrupt Enable Status/Clear Register (IENSTAT) ......................................................... 108
6.3.5 Interrupt Enable Set Register (IENSET) ..................................................................... 109
6.3.6 Interrupt Enable Clear Register (IENCLR) ................................................................... 109
6.3.7 Fixed Range Start Address Register (FXD_MPSAR) ...................................................... 110
6.3.8 Fixed Range End Address Register (FXD_MPEAR) ....................................................... 110
6.3.9 Fixed Range Memory Protection Page Attributes Register (FXD_MPPA) .............................. 111
6.3.10 Programmable Range n Start Address Registers (PROGn_MPSAR) .................................. 112
6.3.11 Programmable Range n End Address Registers (PROGn_MPEAR) ................................... 113
6.3.12 Programmable Range n Memory Protection Page Attributes Register (PROGn_MPPA) ............ 114
6.3.13 Fault Address Register (FLTADDRR) ....................................................................... 115
6.3.14 Fault Status Register (FLTSTAT) ............................................................................ 116
6.3.15 Fault Clear Register (FLTCLR) .............................................................................. 117
7 Device Clocking ............................................................................................................... 119
7.1 Overview .................................................................................................................. 120
7.2 Frequency Flexibility ..................................................................................................... 122
7.3 Peripheral Clocking ...................................................................................................... 123
7.3.1 USB Clocking .................................................................................................... 123
7.3.2 DDR2/mDDR Memory Controller Clocking .................................................................. 124
7.3.3 EMIFA Clocking ................................................................................................. 125
7.3.4 EMAC Clocking .................................................................................................. 126
7.3.5 McASP Clocking ................................................................................................ 127
7.3.6 I/O Domains ..................................................................................................... 128
8 Phase-Locked Loop Controller (PLLC) ............................................................................... 129
8.1 Introduction ............................................................................................................... 130
8.2 PLL Controllers ........................................................................................................... 130
8.2.1 Device Clock Generation ....................................................................................... 132
8.2.2 Steps for Programming the PLLs ............................................................................. 133
8.3 PLLC Registers ........................................................................................................... 135
8.3.1 PLLC0 Revision Identification Register (REVID) ........................................................... 136
8.3.2 PLLC1 Revision Identification Register (REVID) ........................................................... 137
8.3.3 Reset Type Status Register (RSTYPE) ...................................................................... 137
8.3.4 PLLC0 Reset Control Register (RSCTRL) ................................................................... 138
8.3.5 PLLC0 Control Register (PLLCTL) ........................................................................... 139
8.3.6 PLLC1 Control Register (PLLCTL) ........................................................................... 140
8.3.7 PLLC0 OBSCLK Select Register (OCSEL) .................................................................. 141
8.3.8 PLLC1 OBSCLK Select Register (OCSEL) .................................................................. 142
8.3.9 PLL Multiplier Control Register (PLLM) ...................................................................... 143
8.3.10 PLLC0 Pre-Divider Control Register (PREDIV) ............................................................ 143
4
Contents SPRUH78A–December 2011
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