################################################################################
# Vivado (TM) v2017.4 (64-bit)
#
# README.txt: Please read the sections below to understand the steps required
# to simulate the design for a simulator, the directory structure
# and the generated exported files.
#
################################################################################
1. Simulate Design
To simulate design, cd to the simulator directory and execute the script.
For example:-
% cd questa
% ./top.sh
The export simulation flow requires the Xilinx pre-compiled simulation library
components for the target simulator. These components are referred using the
'-lib_map_path' switch. If this switch is specified, then the export simulation
will automatically set this library path in the generated script and update,
copy the simulator setup file(s) in the exported directory.
If '-lib_map_path' is not specified, then the pre-compiled simulation library
information will not be included in the exported scripts and that may cause
simulation errors when running this script. Alternatively, you can provide the
library information using this switch while executing the generated script.
For example:-
% ./top.sh -lib_map_path /design/questa/clibs
Please refer to the generated script header 'Prerequisite' section for more details.
2. Directory Structure
By default, if the -directory switch is not specified, export_simulation will
create the following directory structure:-
<current_working_directory>/export_sim/<simulator>
For example, if the current working directory is /tmp/test, export_simulation
will create the following directory path:-
/tmp/test/export_sim/questa
If -directory switch is specified, export_simulation will create a simulator
sub-directory under the specified directory path.
For example, 'export_simulation -directory /tmp/test/my_test_area/func_sim'
command will create the following directory:-
/tmp/test/my_test_area/func_sim/questa
By default, if -simulator is not specified, export_simulation will create a
simulator sub-directory for each simulator and export the files for each simulator
in this sub-directory respectively.
IMPORTANT: Please note that the simulation library path must be specified manually
in the generated script for the respective simulator. Please refer to the generated
script header 'Prerequisite' section for more details.
3. Exported script and files
Export simulation will create the driver shell script, setup files and copy the
design sources in the output directory path.
By default, when the -script_name switch is not specified, export_simulation will
create the following script name:-
<simulation_top>.sh (Unix)
When exporting the files for an IP using the -of_objects switch, export_simulation
will create the following script name:-
<ip-name>.sh (Unix)
Export simulation will create the setup files for the target simulator specified
with the -simulator switch.
For example, if the target simulator is "ies", export_simulation will create the
'cds.lib', 'hdl.var' and design library diectories and mappings in the 'cds.lib'
file.
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risc v 处理器的FPGA实现工程
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使用的vivado2017.04版本创建的工程,完成蜂鸟E203 处理器内核的移植,搭建SOC片上系统。运行在A7的FPGA板卡上。
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risc v 处理器的FPGA实现工程 (658个子文件)
xsim.ini.bak 19KB
elaborate.bat 968B
compile.bat 840B
runme.bat 229B
runme.bat 229B
runme.bat 229B
runme.bat 229B
system.bin 3.65MB
system.bit 3.65MB
system_routed.dcp 7.1MB
system_placed.dcp 5.62MB
system.dcp 4.34MB
system_opt.dcp 4.06MB
reset_sys.dcp 20KB
reset_sys.dcp 20KB
mmcm.dcp 9KB
mmcm.dcp 9KB
mmcm.dcp 9KB
compile.do 928B
compile.do 902B
compile.do 822B
compile.do 804B
compile.do 659B
compile.do 635B
compile.do 594B
compile.do 584B
simulate.do 355B
simulate.do 350B
simulate.do 350B
simulate.do 301B
simulate.do 291B
simulate.do 291B
elaborate.do 227B
simulate.do 195B
simulate.do 185B
elaborate.do 173B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
simulate.do 11B
simulate.do 11B
run.f 557B
run.f 374B
usage_statistics_webtalk.html 40KB
xsim.ini 19KB
xsim.ini 19KB
xsim.ini 19KB
vivado_16916.backup.jou 3KB
vivado.jou 2KB
vivado_3816.backup.jou 1KB
vivado_5304.backup.jou 1019B
vivado.jou 751B
vivado_6048.backup.jou 727B
vivado_9984.backup.jou 727B
vivado.jou 717B
vivado_15708.backup.jou 715B
vivado.jou 714B
vivado_2492.backup.jou 714B
vivado.jou 710B
ISEWrap.js 7KB
ISEWrap.js 7KB
ISEWrap.js 7KB
ISEWrap.js 7KB
rundef.js 1KB
rundef.js 1KB
rundef.js 1KB
rundef.js 1KB
.reset_sys.xcix.lock 0B
.mmcm.xcix.lock 0B
runme.log 473KB
runme.log 80KB
runme.log 26KB
runme.log 26KB
runme.log 21KB
runme.log 20KB
runme.log 20KB
vivado_16916.backup.log 7KB
vivado.log 5KB
vivado_3816.backup.log 4KB
vivado_5304.backup.log 2KB
compile.log 2KB
xvlog.log 2KB
elaborate.log 2KB
ip_upgrade.log 1KB
vivado_6048.backup.log 1KB
vivado_9984.backup.log 1KB
xvhdl.log 207B
project_1.lpr 343B
elab.opt 232B
elab.opt 178B
fsm_encoding.os 999B
vivado.pb 841KB
place_design.pb 57KB
write_bitstream.pb 50KB
vivado.pb 45KB
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