Workshop Topics
C2000 MCU 1-Day Workshop 3
Workshop Topics
Workshop Topics ......................................................................................................................... 3
Workshop Introduction ................................................................................................................. 5
Outline ...................................................................................................................................... 5
Required Workshop Materials .................................................................................................. 6
F28379D LaunchPad ............................................................................................................... 6
F28x7x Piccolo / Delfino Comparison ...................................................................................... 7
Architectural Overview ................................................................................................................. 8
F2837xD Block Diagram .......................................................................................................... 8
Simplified F28x7x Memory Map ............................................................................................... 9
Interrupt Response Manager ................................................................................................. 10
Direct Memory Access (DMA) ................................................................................................ 10
Control Law Accelerator (CLA) .............................................................................................. 11
Viterbi / Complex Math Unit (VCU) ........................................................................................ 11
Trigonometric Math Unit (TMU).............................................................................................. 12
External Memory Interface (EMIF) ......................................................................................... 12
Communication Peripherals ................................................................................................... 13
On-Chip Safety Features ....................................................................................................... 13
Programming Development Environment .................................................................................. 14
Programming Model ............................................................................................................... 14
Code Composer Studio .......................................................................................................... 15
Software Development and COFF Concepts ......................................................................... 15
Edit and Debug Perspective................................................................................................... 17
Target Configuration .............................................................................................................. 18
CCS Project and Build Options .............................................................................................. 19
CCSv6 Debug Environment ................................................................................................... 22
Dual Subsystem Debug ......................................................................................................... 24
Lab File Directory Structure ................................................................................................... 25
Lab 1: Dual-Core Debug with F2837xD ..................................................................................... 26
Reset, Interrupts and System Initialization................................................................................. 33
Reset Sources ........................................................................................................................ 33
Boot Process .......................................................................................................................... 33
Emulation Boot Mode ............................................................................................................. 34
Stand-Alone Boot Mode ......................................................................................................... 35
Reset Code Flow – Summary ................................................................................................ 36
Interrupt Sources .................................................................................................................... 36
Peripheral Interrupt Expansion – PIE ..................................................................................... 38
F2837xD PIE Assignment Table ............................................................................................ 38
PIE Block Initialization ............................................................................................................ 40
F2837xD Dual-Core Interrupt Structure ................................................................................. 41
F28x7x Oscillator / PLL Clock Module ................................................................................... 42
Watchdog Timer Module ........................................................................................................ 43
F28x7x General-Purpose Input-Output .................................................................................. 44
GPIO Input X-Bar ................................................................................................................... 45
GPIO Output X-Bar ................................................................................................................ 46
Analog Subsystem ..................................................................................................................... 48
ADC Subsystem ..................................................................................................................... 48
ADC Module Block Diagram .................................................................................................. 49
ADC Triggering ...................................................................................................................... 50
ADC Conversion Priority ........................................................................................................ 51
Post Processing Block ........................................................................................................... 52
Comparator Subsystem ......................................................................................................... 54
