5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Boot Mode Select
Boot Mode
Cascade JTAG
TF Card
QSPI Flash
JP4JP1 JP2 JP3
0 0 0 0
0 1 0 1
0 0 0 1
NOR Flash
NAND Flash
0 0 01
0 0 01
V3P3
V3P3
V3P3
V3P3
PS_MIO2_NAND_ALE 3,10
PS_MIO4_NAND_DQ2 3,10
PS_MIO3_NAND_WE# 3,10
PS_MIO5_NAND_DQ0 3,10
Title
Size Document Number Rev
Date: Sheet of
<Doc> V1.0
AntMiner_ControlBoard_XC7010
A
1 15Friday, July 01, 2016
Title
Size Document Number Rev
Date: Sheet of
<Doc> V1.0
AntMiner_ControlBoard_XC7010
A
1 15Friday, July 01, 2016
Title
Size Document Number Rev
Date: Sheet of
<Doc> V1.0
AntMiner_ControlBoard_XC7010
A
1 15Friday, July 01, 2016
20KR3
JP2
SIP_2.54mm
1
1
2
2
3
3
20KR2
JP3
SIP_2.54mm
1
1
2
2
3
3
20KR1
20KR4
JP1
SIP_2.54mm
1
1
2
2
3
3
JP4
SIP_2.54mm
1
1
2
2
3
3
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
BANK 0
PS_SRST# JTAG_RST#
JTAG_TMS
JTAG_TCK
JTAG_TDO
JTAG_TDI
JTAG_RST#
DONE
JTAG_TCK
JTAG_TMS
JTAG_TDI
JTAG_TDO
DONE
V3P3
V2P5
V1P8
V3P3
V2P5
V3P3
V3P3
V3P3
V3P3
V3P3
V2P5
V3P3
V3P3
PS_SRST#4
PS_MIO47_KEY_RESET4
Title
Size Document Number Rev
Date: Sheet of
<Doc> V1.0
AntMiner_ControlBoard_XC7010
A
2 15Friday, July 01, 2016
Title
Size Document Number Rev
Date: Sheet of
<Doc> V1.0
AntMiner_ControlBoard_XC7010
A
2 15Friday, July 01, 2016
Title
Size Document Number Rev
Date: Sheet of
<Doc> V1.0
AntMiner_ControlBoard_XC7010
A
2 15Friday, July 01, 2016
1KR20
4.7KR10
4.7KR6
C5 0.47uF
C8 0.1uF
C1 10uF
0R14
4.7KR11
220R17
FB2
100R/3A
C6 0.1uF
1KR19
330R182
C2 0.1uF
4.7KR5
U2
LSF0102DCTR
GND
1
Vref_A
2
A1
3
A2
4
B2
5
B1
6
Vref_B
7
EN
8
4.7KR8
S1
KMR231GLFS
1 2
3 4
C3 0.1uF
HEADER 2X7
J10
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
0R9
C4 0.1uF
0 R23
0
R16
4.7KR15
4.7KR7
C7 0.1uF
0R12
200KR21
FB1
100R/3A
4.7KR22
0R13
0 NCR24
U1A
xc7z010clg400_10
DONE_0
R11
DXP_0
M9
GNDADC_0
J10
VCCADC_0
J9
VREFP_0
L9
VN_0
L10
VCCBATT_0
F11
TCK_0
F9
DXN_0
M10
VREFN_0
K10
VP_0
K9
RSVDGND
F10
RSVDVCC3
N6
RSVDVCC2
R6
INIT_B_0
R10
TDI_0
G6
TDO_0
F6
RSVDVCC1
T6
CFGBVS_0
M6
PROGRAM_B_0
L6
TMS_0
J6
VCCO_0
K6
0R18
G
D
S
Q4
2N7002-7-F
SOT23_3
D1
G/25mA/0603
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
PLL ENABLED
BANK500
：
3.3V
BANK501
：
2.5V
BANK 500
During an SD memory card boot sequence, the BootROM
reads the logic level on the MIO pin 0 as an SD Card
Detect. MIO pin 0 must be Low during the SDIO boot
process.
PS_MIO8_NAND_RE#
PS_MIO7_NAND_CLE
PS_MIO6_NAND_DQ1
PS_CLK_33M33
PS_MIO0_NAND_CS#
PS_MIO15_LED
PS_MIO14_NAND_R/B#
PS_MIO1_NAND_WP#
PS_MIO0_NAND_CS#
V3P3
V3P3
V3P3
V3P3
P_GOOD12,15
PS_MIO0_NAND_CS# 10
PS_MIO2_NAND_ALE 1,10
PS_MIO3_NAND_WE# 1,10
PS_MIO7_NAND_CLE 10
PS_MIO8_NAND_RE# 10
PS_MIO14_NAND_R/B# 10
PS_MIO4_NAND_DQ2 1,10
PS_MIO5_NAND_DQ0 1,10
PS_MIO6_NAND_DQ1 10
PS_MIO9_NAND_DQ4 10
PS_MIO10_NAND_DQ5 10
PS_MIO11_NAND_DQ6 10
PS_MIO12_NAND_DQ7 10
PS_MIO13_NAND_DQ3 10
PS_MIO1_NAND_WP# 10
Title
Size Document Number Rev
Date: Sheet of
<Doc> V1.0
AntMiner_ControlBoard_XC7010
A
3 15Friday, July 01, 2016
Title
Size Document Number Rev
Date: Sheet of
<Doc> V1.0
AntMiner_ControlBoard_XC7010
A
3 15Friday, July 01, 2016
Title
Size Document Number Rev
Date: Sheet of
<Doc> V1.0
AntMiner_ControlBoard_XC7010
A
3 15Friday, July 01, 2016
C9 0.1uF
D2
G/25mA/0603
C12 0.1uF
20KR30
33R26
C13 0.1uF
1KR188
U1B
xc7z010clg400_10
PS_POR_B_500
C7
PS_MIO15_500
C8
PS_CLK_500
E7
PS_MIO13_500
E8
PS_MIO12_500
D9
PS_MIO11_500
C6
PS_MIO10_500
E9
PS_MIO9_500
B5
PS_MIO8_500
D5
PS_MIO7_500
D8
PS_MIO6_500
A5
PS_MIO5_500
A6
PS_MIO4_500
B7
PS_MIO3_500
D6
PS_MIO2_500
B8
PS_MIO1_500
A7
PS_MIO0_500
E6
VCCO_MIO0_500_1
B6
VCCO_MIO0_500_2
D7
PS_MIO14_500
C5
20KR29
1KR187
C10 100uF
1KR189
Y1
33..330MHz
ENA/DSI
1
GND
2
OUT
3
VCC
4
220R27
20KR175
20KR28
4.7KR25
C11 10uF
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
BANK 501
PS_MIO37_LED_R
PS_MIO38_LED_G
PS_MIO39_BEEP
ETH_MDC
ETH_MDIO
PS_MIO51_IP_GET
PS_MIO39_BEEP
PS_MIO51_IP_GET
PS_MIO38_LED_G
PS_MIO37_LED_R
V2P5
V2P5
V2P5
V3P3 V2P5
V3P3
ETH_TX_CLK12
ETH_TXD012
ETH_TXD112
ETH_TXD212
ETH_TXD312
ETH_TX_CTRL12
ETH_RX_CLK12
ETH_RX012
ETH_RX112
ETH_RX212
ETH_RX312
ETH_RX_CTRL12
PS_MIO28_EN1 13
PS_MIO29_EN2 13
PS_MIO30_EN3 13
PS_MIO31_EN4 13
PS_MIO32_EN5 13
PS_MIO33_EN6 13
PS_MIO34_EN7 13
PS_MIO35_EN8 13
ETH_MDC 12
ETH_MDIO 12
PS_MIO40_CD_CLK 11
PS_MIO41_CD_CMD 11
PS_MIO42_CD_D0 11
PS_MIO43_CD_D1 11
PS_MIO44_CD_D2 11
PS_MIO45_CD_D3 11
PS_MIO46_CD_SW 11
PS_MIO50_CD_WP 11
PS_MIO36_EN9 13
PS_SRST#2
PS_MIO47_KEY_RESET 2
MIO49_UART_RXD 11
MIO48_UART_TXD 11
Title
Size Document Number Rev
Date: Sheet of
<Doc> V1.0
AntMiner_ControlBoard_XC7010
A
4 15Friday, July 01, 2016
Title
Size Document Number Rev
Date: Sheet of
<Doc> V1.0
AntMiner_ControlBoard_XC7010
A
4 15Friday, July 01, 2016
Title
Size Document Number Rev
Date: Sheet of
<Doc> V1.0
AntMiner_ControlBoard_XC7010
A
4 15Friday, July 01, 2016
33R31
G
D
S
Q2
2N7002-7-F
SOT23_3
C20 0.1uF
220R35
C16 0.1uF
1KR37
220R34
C17 0.1uF
S2
KMR231GLFS
1 2
3 4
1KR32
1KR38
G
D
S
Q3
2N7002-7-F
SOT23_3
C18 0.1uF
Q1
MMBT3904
1KR33
D3
F5G1
1
3
2
4
U1C
xc7z010clg400_10
PS_MIO_VREF_501
E11
PS_MIO40_501
D14
PS_MIO46_501
D16
PS_MIO48_501
B12
PS_MIO50_501
B13
PS_MIO52_501
C10
PS_SRST_B_501
B10
VCCO_MIO1_501_1
A13
VCCO_MIO1_501_2
B16
VCCO_MIO1_501_3
D12
VCCO_MIO1_501_4
E15
PS_MIO41_501
C17
PS_MIO43_501
A9
PS_MIO45_501
B15
PS_MIO42_501
E12
PS_MIO44_501
F13
PS_MIO29_501
C13
PS_MIO31_501
E16
PS_MIO33_501
D15
PS_MIO35_501
F12
PS_MIO38_501
E13
PS_MIO16_501
A19
PS_MIO28_501
C16
PS_MIO30_501
C15
PS_MIO32_501
A14
PS_MIO36_501
A11
PS_MIO37_501
A10
PS_MIO39_501
C18
PS_MIO47_501
B14
PS_MIO49_501
C12
PS_MIO51_501
B9
PS_MIO53_501
C11
PS_MIO17_501
E14
PS_MIO18_501
B18
PS_MIO19_501
D10
PS_MIO20_501
A17
PS_MIO21_501
F14
PS_MIO22_501
B17
PS_MIO23_501
D11
PS_MIO24_501
A16
PS_MIO25_501
F15
PS_MIO26_501
A15
PS_MIO27_501
D13
PS_MIO34_501
A12
C15 10uF
C19 0.1uF
4.7KR36
BZ1
Bell
1
2
C14 100uF
1KR39
D4
1N4148
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
BANK 502
V1P5
VREF_DDR3
V1P5
V1P5
DDR3_DQS0_P 9
DDR3_DQS1_P 9
DDR3_DQS2_P 9
DDR3_DQS3_P 9
DDR3_DQS0_N 9
DDR3_DQS1_N 9
DDR3_DQS2_N 9
DDR3_DQS3_N 9
DDR3_RESET# 9
DDR3_BA09
DDR3_BA19
DDR3_BA29
DDR3_CAS#9
DDR3_RAS#9
DDR3_WE#9
DDR3_CS#9
DDR3_CLK_P9
DDR3_CLK_N9
DDR3_CKE9
DDR3_ODT9
DDR3_DM0 9
DDR3_DM1 9
DDR3_DM2 9
DDR3_DM3 9
DDR3_DQ0 9
DDR3_DQ1 9
DDR3_DQ2 9
DDR3_DQ3 9
DDR3_DQ4 9
DDR3_DQ5 9
DDR3_DQ6 9
DDR3_DQ7 9
DDR3_DQ8 9
DDR3_DQ9 9
DDR3_DQ10 9
DDR3_DQ11 9
DDR3_DQ12 9
DDR3_DQ13 9
DDR3_DQ14 9
DDR3_DQ15 9
DDR3_DQ16 9
DDR3_DQ17 9
DDR3_DQ18 9
DDR3_DQ19 9
DDR3_DQ20 9
DDR3_DQ21 9
DDR3_DQ22 9
DDR3_DQ23 9
DDR3_DQ24 9
DDR3_DQ25 9
DDR3_DQ26 9
DDR3_DQ27 9
DDR3_DQ28 9
DDR3_DQ29 9
DDR3_DQ30 9
DDR3_DQ31 9
DDR3_A09
DDR3_A19
DDR3_A29
DDR3_A39
DDR3_A49
DDR3_A59
DDR3_A69
DDR3_A79
DDR3_A89
DDR3_A99
DDR3_A109
DDR3_A119
DDR3_A129
DDR3_A139
DDR3_A149
Title
Size Document Number Rev
Date: Sheet of
<Doc> V1.0
AntMiner_ControlBoard_XC7010
A
5 15Friday, July 01, 2016
Title
Size Document Number Rev
Date: Sheet of
<Doc> V1.0
AntMiner_ControlBoard_XC7010
A
5 15Friday, July 01, 2016
Title
Size Document Number Rev
Date: Sheet of
<Doc> V1.0
AntMiner_ControlBoard_XC7010
A
5 15Friday, July 01, 2016
80.6R40
C21 0.1uF
80.6R41
C33 0.1uF
C24 100uF
C23 100uF
C28 0.1uF
C29 0.1uF
C30 0.1uF
U1D
xc7z010clg400_10
PS_DDR_DRST_B_502
B4
PS_DDR_VRN_502
G5
PS_DDR_VRP_502
H5
PS_DDR_CKP_502
L2
PS_DDR_CKN_502
M2
PS_DDR_BA2_502
J5
PS_DDR_BA1_502
R4
PS_DDR_BA0_502
L5
PS_DDR_ODT_502
N5
PS_DDR_CS_B_502
N1
PS_DDR_CKE_502
N3
PS_DDR_WE_B_502
M5
PS_DDR_CAS_B_502
P5
PS_DDR_RAS_B_502
P4
VCCO_DDR_502_A
A3
VCCO_DDR_502_9
D2
VCCO_DDR_502_8
E5
VCCO_DDR_502_7
G1
VCCO_DDR_502_6
H4
VCCO_DDR_502_5
L3
VCCO_DDR_502_4
P2
VCCO_DDR_502_3
R5
VCCO_DDR_502_2
U1
VCCO_DDR_502_1
V4
PS_DDR_VREF0_502
H6
PS_DDR_VREF1_502
P6
PS_DDR_DQ0_502
C3
PS_DDR_DQ1_502
B3
PS_DDR_DQ2_502
A2
PS_DDR_DQ3_502
A4
PS_DDR_DQ4_502
D3
PS_DDR_DQ5_502
D1
PS_DDR_DQ6_502
C1
PS_DDR_DQ7_502
E1
PS_DDR_DQ8_502
E2
PS_DDR_DQ9_502
E3
PS_DDR_DQ10_502
G3
PS_DDR_DQ11_502
H3
PS_DDR_DQ12_502
J3
PS_DDR_DQ13_502
H2
PS_DDR_DQ14_502
H1
PS_DDR_DQ15_502
J1
PS_DDR_DQ16_502
P1
PS_DDR_DQ17_502
P3
PS_DDR_DQ18_502
R3
PS_DDR_DQ19_502
R1
PS_DDR_DQ20_502
T4
PS_DDR_DQ21_502
U4
PS_DDR_DQ22_502
U2
PS_DDR_DQ23_502
U3
PS_DDR_DQ24_502
V1
PS_DDR_DQ25_502
Y3
PS_DDR_DQ26_502
W1
PS_DDR_DQ27_502
Y4
PS_DDR_DQ28_502
Y2
PS_DDR_DQ29_502
W3
PS_DDR_DQ30_502
V2
PS_DDR_DQ31_502
V3
PS_DDR_A0_502
N2
PS_DDR_A1_502
K2
PS_DDR_A2_502
M3
PS_DDR_A3_502
K3
PS_DDR_A4_502
M4
PS_DDR_A5_502
L1
PS_DDR_A6_502
L4
PS_DDR_A7_502
K4
PS_DDR_A8_502
K1
PS_DDR_A9_502
J4
PS_DDR_A10_502
F5
PS_DDR_A11_502
G4
PS_DDR_A12_502
E4
PS_DDR_A13_502
D4
PS_DDR_A14_502
F4
PS_DDR_DQS_P0_502
C2
PS_DDR_DQS_N0_502
B2
PS_DDR_DQS_P1_502
G2
PS_DDR_DQS_N1_502
F2
PS_DDR_DQS_P2_502
R2
PS_DDR_DQS_N2_502
T2
PS_DDR_DQS_P3_502
W5
PS_DDR_DQS_N3_502
W4
PS_DDR_DM0_502
A1
PS_DDR_DM1_502
F1
PS_DDR_DM2_502
T1
PS_DDR_DM3_502
Y1
C25 10uF
C31 0.1uF
C26 10uF
80.6R42
C32 0.1uFC22 0.1uF
C27 10uF
- 1
- 2
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