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Xilinx FPGA DDR4 接口应用分析
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2018-03-15
17:31:40
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该文件是FPGA中运用DDR4的接口应用解析,分析了FPGA和DDR4之间的连接
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High Performance DDR4 interfaces with
FPGA Flexibility
Adrian Cosoroaba and Terry Magee
Xilinx, Inc.
© Copyright 2014 Xilinx
.
System Requirements for FPGA based systems
– Higher Bandwidth, Increased Flexibility, Lower Power
UltraScale FPGA Solution for DDR4 and other parallel
memory interfaces
PHY Solution for higher performance with maximum
flexibility
Multiple Solutions for Different Needs
AGENDA
© Copyright 2014 Xilinx
.
Rapid growth in serial I/O bandwidth is enabling next generation systems
External memory buffering rate must match or exceed traffic rate
Page 3
Bandwidth Driven Systems Demand Extensive
Memory Buffering
8x8 Multi-
Mode Radio
Semiconductor
ATE
Super Hi-
Vision Camera
Radar
Processing
Medical
Imaging
100G/200G
Networking
© Copyright 2014 Xilinx
.
Data rate per bit
Number of Interfaces (improves with better usage of I/O)
Data bus width
Data bus efficiency (percentage of time that data bus is utilized)
Page 4
FPGA Memory Interface Bandwidth
© Copyright 2014 Xilinx
.
30% higher data rates vs. DDR3
– 2400 Mb/s (UltraScale devices) vs. 1866 Mb/s (7 series devices)
Available in both mid- and high-speed grade
– Lower cost benefits of a flexible architecture
Higher DDR4 Data Rates
1200
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1600
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2200
2400
2600
2800
2010
2011
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2014
2015
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- Captain_船长2018-09-18纯粹是骗人的
- 九章子2018-03-24不要下载,骗人的,这是网络上的一篇文档,讲解的是ddr3与ddr4在io设计上不同之处
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