英飞凌XMC4500串口代码

/**************************************************************************//** * @file system_XMC4500.c * @brief CMSIS Cortex-M4 Device Peripheral Access Layer Header File * for the Infineon XMC4500 Device Series * @version V3.0.1 Alpha * @date 17. September 2012 * * @note * Copyright (C) 2011 ARM Limited. All rights reserved. * * @par * ARM Limited (ARM) is supplying this software for use with Cortex-M * processor based microcontrollers. This file can be freely distributed * within development tools that are supporting such ARM based processors. * * @par * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. * ******************************************************************************/ #include "system_XMC4500.h" #include <XMC4500.h> /*---------------------------------------------------------------------------- Clock Variable definitions *----------------------------------------------------------------------------*/ /*!< System Clock Frequency (Core Clock)*/ uint32_t SystemCoreClock; /* clock definitions, do not modify! */ #define SCU_CLOCK_CRYSTAL 1 #define SCU_CLOCK_BACK_UP_FACTORY 2 #define SCU_CLOCK_BACK_UP_AUTOMATIC 3 #define HIB_CLOCK_FOSI 1 #define HIB_CLOCK_OSCULP 2 /* //-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ */ /*--------------------- Watchdog Configuration ------------------------------- // // <e> Watchdog Configuration // <o1.0> Disable Watchdog // // </e> */ #define WDT_SETUP 1 #define WDTENB_nVal 0x00000001 /*--------------------- CLOCK Configuration ------------------------------- // // <e> Main Clock Configuration // <o1.0..1> CPU clock divider // <0=> fCPU = fSYS // <1=> fCPU = fSYS / 2 // <o2.0..1> Peripheral Bus clock divider // <0=> fPB = fCPU // <1=> fPB = fCPU / 2 // <o3.0..1> CCU Bus clock divider // <0=> fCCU = fCPU // <1=> fCCU = fCPU / 2 // // </e> // */ #define SCU_CLOCK_SETUP 1 #define SCU_CPUCLKCR_DIV 0x00000000 #define SCU_PBCLKCR_DIV 0x00000000 #define SCU_CCUCLKCR_DIV 0x00000000 /* not avalible in config wizzard*/ /* * mandatory clock parameters ************************************************** * * source for clock generation * range: SCU_CLOCK_CRYSTAL (crystal or external clock at crystal input) * **************************************************************************************/ // Selection of imput lock for PLL /*************************************************************************************/ #define SCU_PLL_CLOCK_INPUT SCU_CLOCK_CRYSTAL //#define SCU_PLL_CLOCK_INPUT SCU_CLOCK_BACK_UP_FACTORY //#define SCU_PLL_CLOCK_INPUT SCU_CLOCK_BACK_UP_AUTOMATIC /*************************************************************************************/ // Standby clock selection for Backup clock source trimming /*************************************************************************************/ #define SCU_STANDBY_CLOCK HIB_CLOCK_OSCULP //#define SCU_STANDBY_CLOCK HIB_CLOCK_FOSI /*************************************************************************************/ // Global clock parameters /*************************************************************************************/ #define CLOCK_FSYS 120000000 #define CLOCK_CRYSTAL_FREQUENCY 12000000 #define CLOCK_BACK_UP 24000000 /*************************************************************************************/ /* OSC_HP setup parameters */ /*************************************************************************************/ #define SCU_OSC_HP_MODE 0xF0 #define SCU_OSCHPWDGDIV 2 /*************************************************************************************/ /* MAIN PLL setup parameters */ /*************************************************************************************/ //Divider settings for external crystal @ 12 MHz /*************************************************************************************/ #define SCU_PLL_K1DIV 1 #define SCU_PLL_K2DIV 3 #define SCU_PLL_PDIV 1 #define SCU_PLL_NDIV 79 /*************************************************************************************/ //Divider settings for use of backup clock source trimmed /*************************************************************************************/ //#define SCU_PLL_K1DIV 1 //#define SCU_PLL_K2DIV 3 //#define SCU_PLL_PDIV 3 //#define SCU_PLL_NDIV 79 /*************************************************************************************/ /*--------------------- USB CLOCK Configuration --------------------------- // // <e> USB Clock Configuration // // </e> // */ #define SCU_USB_CLOCK_SETUP 0 /* not avalible in config wizzard*/ #define SCU_USBPLL_PDIV 0 #define SCU_USBPLL_NDIV 31 #define SCU_USBDIV 3 /*--------------------- Flash Wait State Configuration ------------------------------- // // <e> Flash Wait State Configuration // <o1.0..3> Flash Wait State // <0=> 3 WS // <1=> 4 WS // <2=> 5 WS // <3=> 6 WS // </e> // */ #define PMU_FLASH 1 #define PMU_FLASH_WS 0x00000000 /*--------------------- CLOCKOUT Configuration ------------------------------- // // <e> Clock OUT Configuration // <o1.0..1> Clockout Source Selection // <0=> System Clock // <2=> Divided value of USB PLL output // <3=> Divided value of PLL Clock // <o2.0..4> Clockout divider <1-10><#-1> // <o3.0..1> Clockout Pin Selection // <0=> P1.15 // <1=> P0.8 // // // </e> // */ #define SCU_CLOCKOUT_SETUP 0 #define SCU_CLOCKOUT_SOURCE 0x00000003 #define SCU_CLOCKOUT_DIV 0x00000009 #define SCU_CLOCKOUT_PIN 0x00000001 /*---------------------------------------------------------------------------- Clock Variable definitions *----------------------------------------------------------------------------*/ /*!< System Clock Frequency (Core Clock)*/ #if SCU_CLOCK_SETUP uint32_t SystemCoreClock = CLOCK_FSYS; #else uint32_t SystemCoreClock = CLOCK_BACK_UP; #endif /*---------------------------------------------------------------------------- static functions declarations *----------------------------------------------------------------------------*/ #if (SCU_CLOCK_SETUP == 1) static int SystemClockSetup(void); #endif #if (SCU_USB_CLOCK_SETUP == 1) static int USBClockSetup(void); #endif /** * @brief Setup the microcontroller system. * Initialize the PLL and update the * SystemCoreClock variable. * @param None * @retval None */ void SystemInit(void) { int temp; #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) SCB->CPACR |= ((3UL << 10*2) | /* set CP10 Full Access */ (3UL << 11*2) ); /* set CP11 Full Access */ #endif /* Enable unaligned memory access - SCB_CCR.UNALIGN_TRP = 0 */ SCB->CCR &= ~(SCB_CCR_UNALIGN_TRP_Msk); /* Setup the WDT */ #if WDT_SETUP WDT->CTR &= ~WDTENB_nVal; #endif /* Setup the Flash Wait State */ #if PMU_FLASH temp = FLASH0->FCON; temp &= ~FLASH_FCON_WSPFLASH_Msk; temp |= PMU_FLASH_WS+3; FLASH0->FCON = temp; #endif /* Setup the clockout */ #if SCU_CLOCKOUT_SETUP SCU_CLK->EXTCLKCR |= SCU_CLOCKOUT_SOURCE;