UVM 验证测试平台搭建简单示例（详细）
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Copyright 2011 by Doulos Ltd. All rights reserved. All information is provided “as is” without warranty of any kind. 1
Easier UVM for Functional Verification by Mainstream Users
Updated and Extended for UVM 1.0
John Aynsley
Doulos
Church Hatch, 22 Market Place
Ringwood, United Kingdom
+44 1425 471223
john.aynsley@doulos.com
ABSTRACT
This paper describes an approach to using Accellera's UVM, the
Universal Verification Methodology, for functional verification by
mainstream users. The goal is to identify a minimal set of concepts
sufficient for constrained random coverage-driven verification in
order to ease the learning experience for engineers coming from a
hardware design background who do not have extensive object-
oriented programming skills. We describe coding guidelines to
address the canonical structure of a UVM component and a UVM
transaction, the construction of the UVM component hierarchy, the
interface with the design-under-test, the use of UVM sequences, and
the use of the factory and configuration mechanisms.
Keywords
SystemVerilog, UVM, functional verification
1. INTRODUCTION
This paper describes an approach to using Accellera's UVM, the
Universal Verification Methodology, for functional verification by
mainstream users as opposed to highly skilled verification
specialists. It arises from experience at Doulos in teaching
SystemVerilog and functional verification methodology to engineers
from a broad cross-section of the hardware design and verification
community. While much of the research and development in
functional verification methodology is rightly focussed on the needs
of power users as they solve the hardest verification problems, we
find that the majority of mainstream users have a somewhat different
focus, namely, how to become productive with SystemVerilog with a
minimum of delay and specialist programming expertise.
SystemVerilog and UVM provide mechanisms to create verification
components for checking, coverage collection, and stimulus
generation, and to modify the behavior of those components for
specific tests. But SystemVerilog and UVM provide more than this,
so much more in fact that the learning curve can be daunting for non-
specialists.
The goal of this paper is to enable engineers with experience in
Verilog or VHDL to become productive in UVM by learning a small
number of new coding idioms, selected to minimize the conceptual
clutter they have to deal with. As users become fluent with this set of
basic idioms, they can then branch out to embrace the full feature set
of UVM as and when they need.
We describe coding guidelines to address the canonical structure of a
UVM component and a UVM transaction, the construction of the
UVM component hierarchy, the interface with the design-under-test,
the use of UVM sequences, and the use of the factory and
configuration mechanisms. Starting from these simple guidelines,
engineers can create constrained random verification environments
in an object-oriented coding style that are fully compliant with the
UVM standard, and hence are interoperable with UVM verification
IP from other sources.
2. EASIER UVM?
Easier UVM is not yet another verification methodology. It is UVM.
The point is to somewhat restrict the range of features being used in
order to make life easier for the novice. This exercise is primarily a
pedagogical one. The aim is to ease the task of learning UVM, not to
deny users the ability to exploit the full power of the UVM class
library. The coding guidelines we give here are not the only ways of
using UVM, nor are they necessarily the best approach for
experienced verification engineers.
Easier UVM does not mean easy UVM. The set of concepts
presented below is still quite extensive and very rich. It is being
increasingly recognized that both system modeling and functional
verification require a high level of software programming skill, and
on top of that, UVM also requires a deep understanding of coverage-
driven verification and transaction-level modeling.
This paper does not explicitly list every UVM feature. Many useful
features have not been mentioned, some of them essential for
advanced UVM usage, significant examples being report handling
and the end-of-test mechanisms. Easier UVM merely provides a
conceptual foundation on which to build a deeper knowledge of
UVM.
The version of UVM current at the time of writing of the original
paper was the UVM 1.0 Early Adopter release. The paper you are
reading has been updated to reflect the changes made in UVM 1.0,
released in Feb 2011.
3. SYSTEMVERILOG AND UVM
Over the past few years, constrained random coverage-driven
verification has been increasingly adopted as the methodology-of-
choice for simulation-based functional verification to the point where
it is widely used on the largest ASIC projects. SystemVerilog, as the
only industry standard hardware verification language supported
every one of the three largest EDA vendors, has displaced its rival
single-vendor solutions in many companies.
But SystemVerilog is not without its problems. Although current
SystemVerilog implementations are in many ways both mature and
robust, SystemVerilog remains under-specified as a language.
SystemVerilog was an extremely ambitious standardization project
that was undertaken prior to the development of any complete proof-
of-concept implementation, and as a result the IEEE 1800
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