f1c100s 核心板原理图 V2.0版
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2019-09-15
16:31:24
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5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
VO=0.6(1+100K/82K)=1.33V
VO=0.6(1+100K/80K)=1.35V
VO=0.6(1+100K/85K)=1.30V
800mA 1.2V
VO=0.6(1+100K/75K)=1.399V
PRS3015-2R2NT
VO=0.6(1+100K/82K)=1.33V
VO=0.6(1+100K/80K)=1.35V
VO=0.6(1+100K/85K)=1.30V
VO=0.6(1+100K/75K)=1.399V
VRA1
AGND
VRA2
X24MOUT
X24MIN
SPI-CS
SPI-CS
SPI-MISO
SPI-CLK
SPI-MOSI
SVREF
SPI-CS
SPI-MISO
SPI-CLK
SPI-MOSI
X24MOUT
X24MIN
nRESET
HPCOMFB
HPVCC
HPVCC VRA2AVCC VRA1
SVREF
HPCOMFB LRADC0
I2C0_SDA
I2C0_SCL
MICIN
nRESET
SD0_D0
SD0_D1
SD0_D2
SD0_D3
SD0_CLK
SD0_CMD
LCD_HSYNC
LCD_VSYNC
LCD_CLK
LCD_DE
LCD_D21
LCD_D20
LCD_D23
LCD_D22
LCD_D19
LCD_D10
LCD_D11
LCD_D12
LCD_D13
LCD_D14
LCD_D15
LCD_D5
LCD_D4
LCD_D3
LCD_D6
LCD_D7
LRADC0
USB0_DP
USB0_DN
HP_R
HP_L
SD0_D2
SD0_D3
SD0_CLK
SD0_D1
SD0_D0
SD0_CMD
SD0_CD
UART2_TXD
UART2_RXD
RSB_SCL
RSB_SDA
PWM1
I2C0_SDA
I2C0_SCL
UART0_TXD
UART0_RXD
TOUCH_XP
TOUCH_YP
TOUCH_XN
TOUCH_YN
PE10
PE9
PE5
PE12
PE11
AVCC
VDD_IO
GNDGND
VDD_IO
VDD_5V
VDD_DRAM
VDD_CORE
VDD_IO
VDD_IO
VDD_CORE
VDD_IO
VDD_CORE
VDD_IO
VDD_TV
VDD_DRAMVDD_CORE VDD_IO
AGND
VDD_CORE
VDD_IO
VDD_DRAM
VDD_DRAM
VDD_IO
GND
VDD_IOVDD_5V
VDD_IO
VDD_IO AVCC
VDD_IO
VDD_IO
VDD_5V
VDD_IO
VDD_IO
LCD_D10
LCD_D11
LCD_D12
LCD_D13
LCD_D14
LCD_D15
LCD_D19
LCD_D20
LCD_D21
LCD_D22
LCD_D23
LCD_DE
LCD_HSYNC
LCD_VSYNC
LCD_CLK
USB0_DP
USB0_DN
HP_R
LRADC0{8,9}
LCD_D3
LCD_D4
LCD_D5
LCD_D6
LCD_D7
UART0_RXD
UART0_TXD
UART2_TXD
UART2_RXD
PW M1
PE11
PE12
PE9
PE10
PE5
SD0_D1
SD0_D0
SD0_CLK
SD0_CMD
SD0_D3
SD0_D2
SD0_CD
RSB_SDA
RSB_SCL
HP_L TOUCH_XP
TOUCH_XN
TOUCH_YP
TOUCH_YN
Design Name
Size Page Name Rev
Date: Sheet of
AllWinner Technology Co.,Ltd
CPU
V3S_STD_CDR_V1_0
A2
5 12Tuesday, May 14, 2019
Design Name
Size Page Name Rev
Date: Sheet of
AllWinner Technology Co.,Ltd
CPU
V3S_STD_CDR_V1_0
A2
5 12Tuesday, May 14, 2019
Design Name
Size Page Name Rev
Date: Sheet of
AllWinner Technology Co.,Ltd
CPU
V3S_STD_CDR_V1_0
A2
5 12Tuesday, May 14, 2019
C27
0.1u
12
C10
0.1u
C0402
C41
22u
12
C24
22u
12
C2
0.1u
C0402
C38
10n
C0402
C12
4.7u
C0402
R5
0R
R0402
C32
0.1u
C0402
C26
10u
12
C15
0.1u
C0402
C9
0.1u
C0402
C25
10u
12
R4
220K
R0402
R37
100K
C13
0.1u
C0402
L2 CPY160808T-2R2M-NP
1 2
R2
100K
R0402
C166
18pF
C0402
C22
0.1u
C0402
U8
TF_SMD
DATA3
2
DATA2
1
VDD
8
DATA1
7
DATA0
6
CMD
5
GND
4
CLK
3
J6
CON2
1
2
J1
CORE_120PIN_32MM
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
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76
114
114
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113
112
112
111
111
110
110
109
109
108
108
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099
099
098
098
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096
095
095
094
094
093
093
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092
091
091
090
090
089
089
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087
086
086
085
085
084
084
083
083
082
082
081
081
080
080
079
079
078
078
077
077
120
120
119
119
118
118
117
117
116
116
115
115
C167
18pF
C0402
R25
100K
C33
0.1u
C0402C39
10u
12
C21
4.7u
C0402
R10
100K
C1
10u
C0603
C11
0.1u
C0402
R8
2K
R0402
C17
10u
C0603
R1
10K
R0402
U4
W25Q32JVSSIM
CS#
1
MISO
2
WP#
3
VSS
4
MOSI
5
CLK
6
HOLD#
7
VCC
8
C36
0.1u
C0402
C20
4.7u
C0402
C3
0.1u
12
U1
MT3410L
VIN
4
EN
1
GND
2
LX
3
FB
5
C19
1u
C0402
U2
F25
HPL
1
HPCOMFB
2
HPCOM
3
HPVCC
4
VCC_IO
5
PD0/LCD_D2/TWI0_SDA/RSB_SDA
6
PD1/LCD_D3/UART1_RTS
7
PD2/LCD_D4/UART1_CTS
8
PD3/LCD_D5/UART1_RX
9
PD4/LCD_D6/UART1_TX
10
PD5/LCD_D7/TWI1_SCK
11
PD6/LCD_D10/TWI1_SDA
12
PD7/LCD_D11/DA_MCLK
13
PD8/LCD_D12/DA_BCLK
14
PD9/LCD_D13/DA_LRCK
15
PD10/LCD_D14/DA_IN
16
PD11/LCD_D15/DA_OUT
17
PD12/LCD_D18/TWI0_SCK/RSB_SCK
18
PD13/LCD_D19/UART2_TX
19
VCC_IO
20
PD14/LCD_D20/UART2_RX
21
VDD_CORE
22
PD15/LCD_D21/UART2_RTS/TWI2_SCK
23
PD16/LCD_D22/UART2_CTS/TWI2_SDA
24
PD17/LCD_D23/OWA_OUT
25
PD18/LCD_CLK/SPI0_CS
26
PD19/LCD_DE/SPI0_MOSI
27
PD20/LCD_HSYNC/SPI0_CLK
28
PD21/LCD_VSYNC/SPI0_MISO
29
VCC_DRAM
30
VCC_DRAM
31
VCC_DRAM
32
SVREF
33
VCC_DRAM
34
VDD_CORE
35
VCC_DRAM
36
PE12/DA_MCLK_TWI0_SDA/PWM0
37
PE11/CLK_OUT/TWI0_SCK/IR_RX
38
PE10/CSI_D7/UART2_CTS/SPI1_MISO
39
PE9/CSI_D6/UART2_RTS/SPI1_CLK
40
PE8/CSI_D5/UART2_RX/SPI1_MOSI
41
PE7/CSI_D4/UART2_TX/SPI1_CS
42
PE6CSI_D3/PWM1/DA_OUT/OWA_OUT
43
PE5/CSI_D2/LCD_D17/DA_IN
44
PE4/CSI_D1/LCD_D16/DA_LRCK/RSB_SDA
45
PE3/CSI_D0/LCD_D9/DA_BCLK/RS_SCK
46
PE2/CSI_PCLK/LCD_D8/CLK_OUT
47
PE1/CSI_VSYNC/LCD_D1/TWI2_SDA/UART0_TX
48
PE0/CSI_HSYNC/LCD_D0/TWI2_SCK/UART0_RX
49
VCC_IO
50
HOSI
51
HOSCO
52
PF5/SDC0_D2/DBG_CK/PWM1
53
PF4/SDC0_D3/UART0_TX
54
PF3/SDC0_CMD/DBG_DO
55
PF2/SDC0_CLK/UART0_RX
56
PF1/SDC0_D0/DBG_DI
57
PF0/SDC0_D1/DBG_MS/IR_RX
58
PC0/SPI0_CLK/SDC1_CLK
59
PC1/SPI0_CS/SDC1_CMD
60
PC2/SPI0_MISO/SDC1_D0
61
PC3/SPI0_MOSI/UART0_TX
62
PA3/TPY2/IR_RX/DA_OUT/UART1_TX/SPI1_MISO
63
PA2/TPY1/PWM0/DA_IN/UART1_RX/SPI1_CLK
64
PA1/TPX2/DA_LRCK/UART1_CTS/SPI1_MOSI
65
PA0/TPX1/DA_BCLK/UART1_RTS/SPI1_CS
66
UVCC
67
USB_DM
68
USB_DP
69
RESET
70
VDD_CORE
71
TVOUT
72
TV_VCC
73
TVGND
74
TV_VRN
75
TV_VRP
76
TVIN1
77
TVIN0
78
LRADC0
79
AVCC
80
VRA1
81
AGND
82
VRA2
83
FMINL
84
FMINR
85
LINL
86
MICIN
87
HPR
88
EP
89
C18
0.1u
C0402
R9
100K
R0402
U9
MT3410L
VIN
4
EN
1
GND
2
LX
3
FB
5
U3
ME6211C25M5G-N
Vin
1
GND
2
EN
3
BP
4
Vout
5
X1
24MHz
X2
3
GND
2
GND
4
X1
1
C30
0.1u
C0402
C16
0.1u
C0402
R6
2K
R0402
C14
10u
12
U6
CN809S
SOT23
GND
1
RESET
2
VCC
3
L1 CPY160808T-2R2M-NP
1 2
C37
1u
C0402
C42
22p
12
C29
22p
12
U7
LN6206P282MR-G
VIN
3
GND
1
OUT
2
R11
22.1K
资源评论
忧伤的石一2023-07-24这份文件提供了清晰的电路连接图，让人很容易理解该核心板的硬件组成和工作原理。
whph2023-07-24对于初学者来说，这份文件提供了足够的细节，帮助他们了解如何设计和制作自己的核心板。
爱设计的唐老鸭2023-07-24此文件对于了解F1C100s芯片及其相关电路设计提供了不少有用的信息，值得一读。
呆呆美要暴富2023-07-24这份F1C100s核心板原理图 V2.0版文件内容详实，对于学习硬件设计的人来说是一份很好的参考资料。
半清斋2023-07-24虽然这份文件没有过多的深入讲解，但对于了解基本的核心板原理和设计思路足够了，适合初学者入门。
