A new 6-bit 250 MS/s analog-to-digital converter
(ADC) is proposed for low-power low-cost CMOS integrated
systems. This design is based on an improved successive approximation
ADC with a mixed-mode subtracter that minimizes
the overall power consumption and system complexity. The
experimental results indicate that this ADC works up to 250 MS/s
with power consumption less than 30 mW at 3.3 V. Moreover, the
operating voltage is scaled down to 0.8 V using a slight adjustment.
The ADC occupies only 0.1 mm2 with the TSMC 0.35- m single
ploy quadruple metal (SPQM) CMOS technology. This design is
suitable for standard CMOS technology with low-power low-cost
VLSI implementation.
