ANSI/VITA 65-2010 (R2012) Page 4 of 555 February 2012
3.4.7 JTAG Port ............................................................................................................................................. 73
3.4.8 User I/O ................................................................................................................................................ 73
3.4.9 Auxiliary Resets (AXreset*) .................................................................................................................. 74
3.5 SYSTEM REFERENCE CLOCKS ................................................................................................................................ 74
3.5.1 REF_CLK+/- Reference Clock ................................................................................................................ 74
3.5.2 AUX_CLK+/- Reference Clock ............................................................................................................... 75
3.5.3 P1-REF_CLK-SE ..................................................................................................................................... 76
3.6 BUSSED GPIO (GDISCRETE1) .............................................................................................................................. 77
3.7 OPENVPX VITA 46.0 CONNECTOR P0/J0 AND P1/J1 CONNECTOR PIN ASSIGNMENTS ................................................. 78
4 MECHANICAL – GENERAL SPECIFICATIONS ............................................................................................... 82
4.1 SLOT PITCH ...................................................................................................................................................... 82
4.2 CONNECTOR FAMILY .......................................................................................................................................... 83
4.3 KEYING ............................................................................................................................................................ 83
4.4 RTM CONNECTORS ........................................................................................................................................... 84
5 PROTOCOL SPECIFIC ................................................................................................................................ 85
5.1 ETHERNET ........................................................................................................................................................ 85
5.1.1 1000BASE-BX ....................................................................................................................................... 85
5.1.2 1000BASE-KX ........................................................................................................................................ 85
5.1.3 1000BASE-T .......................................................................................................................................... 85
5.1.4 10GBASE-BX4 ....................................................................................................................................... 86
5.1.5 10GBASE-KX4 ....................................................................................................................................... 86
5.1.6 10GBASE-T ........................................................................................................................................... 86
5.2 SERIAL RAPIDIO
®
(SRIO) .................................................................................................................................... 86
5.3 PCI-EXPRESS
®
(PCIE
®
) ..................................................................................................................................... 87
5.3.1 PCIe Gen 2 Common Reference Clock Implemented as REF_CLK on P0/J0 .......................................... 88
5.3.2 PCIe Gen 2 Common Reference Clock Implemented on Other Than REF_CLK pins on P0/J0 ............... 88
5.4 INFINIBAND
®
(IB) .............................................................................................................................................. 92
6 COMMON TO 6U AND 3U — SLOT PROFILES ............................................................................................ 93
6.1 ORDER OF PRECEDENCE ...................................................................................................................................... 93
6.2 COMMON REQUIREMENTS FOR ALL SLOT PROFILES ................................................................................................. 93
6.2.1 Reserved pins ....................................................................................................................................... 93
6.2.2 Which lanes, ports and pins are used (unused = reserved) .................................................................. 94
6.2.3 Plug-In Module Compatibility with Multiple Slot Profiles .................................................................... 94
6.2.4 Assigning Lanes Into Ports ................................................................................................................... 94
6.3 COMMON REQUIREMENTS FOR SLOT PROFILES USING VITA 46.0 CONNECTORS. .......................................................... 99
6.3.1 Pin Assignment Tables for Differential Connectors .............................................................................. 99
6.3.2 Pin Assignment Tables for Single-Ended Connectors ......................................................................... 103
6.3.3 User Defined ...................................................................................................................................... 103
6.4 COMMON REQUIREMENTS FOR SLOT PROFILES USING VITA 46.0 AND VITA 67 CONNECTORS ..................................... 109
6.4.1 Pin Assignment Tables for VITA 46.0 Differential Connectors ........................................................... 109
6.4.2 Pin Assignment Tables for Single-Ended Connectors ......................................................................... 109
6.4.3 User Defined ...................................................................................................................................... 110
7 COMMON TO 6U AND 3U — BACKPLANE PROFILES ................................................................................ 111
7.1 ORDER OF PRECEDENCE .................................................................................................................................... 111
7.2 INTERCONNECTING SLOTS WITH PIPES ................................................................................................................. 111
7.2.1 Slot Profiles Labeled as Lanes ............................................................................................................ 112
7.2.2 Slot Profiles Labeled as Thin Pipe Pairs A thru D ................................................................................ 112
7.3 PORT JUMBLING .............................................................................................................................................. 113
7.4 BACKPLANE CHANNEL GBAUD RATE .................................................................................................................... 113
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