################################################################################
# Vivado (TM) v2015.4.2 (64-bit)
#
# README.txt: Please read the sections below to understand the steps required
# to simulate the design for a simulator, the directory structure
# and the generated exported files.
#
################################################################################
1. Simulate Design
To simulate design, cd to the simulator directory and execute the script.
For example:-
% cd questa
% ./top.sh
The export simulation flow requires the Xilinx pre-compiled simulation library
components for the target simulator. These components are referred using the
'-lib_map_path' switch. If this switch is specified, then the export simulation
will automatically set this library path in the generated script and update,
copy the simulator setup file(s) in the exported directory.
If '-lib_map_path' is not specified, then the pre-compiled simulation library
information will not be included in the exported scripts and that may cause
simulation errors when running this script. Alternatively, you can provide the
library information using this switch while executing the generated script.
For example:-
% ./top.sh -lib_map_path /design/questa/clibs
Please refer to the generated script header 'Prerequisite' section for more details.
2. Directory Structure
By default, if the -directory switch is not specified, export_simulation will
create the following directory structure:-
<current_working_directory>/export_sim/<simulator>
For example, if the current working directory is /tmp/test, export_simulation
will create the following directory path:-
/tmp/test/export_sim/questa
If -directory switch is specified, export_simulation will create a simulator
sub-directory under the specified directory path.
For example, 'export_simulation -directory /tmp/test/my_test_area/func_sim'
command will create the following directory:-
/tmp/test/my_test_area/func_sim/questa
By default, if -simulator is not specified, export_simulation will create a
simulator sub-directory for each simulator and export the files for each simulator
in this sub-directory respectively.
IMPORTANT: Please note that the simulation library path must be specified manually
in the generated script for the respective simulator. Please refer to the generated
script header 'Prerequisite' section for more details.
3. Exported script and files
Export simulation will create the driver shell script, setup files and copy the
design sources in the output directory path.
By default, when the -script_name switch is not specified, export_simulation will
create the following script name:-
<simulation_top>.sh (Unix)
When exporting the files for an IP using the -of_objects switch, export_simulation
will create the following script name:-
<ip-name>.sh (Unix)
Export simulation will create the setup files for the target simulator specified
with the -simulator switch.
For example, if the target simulator is "ies", export_simulation will create the
'cds.lib', 'hdl.var' and design library diectories and mappings in the 'cds.lib'
file.
没有合适的资源?快使用搜索试试~ 我知道了~
资源推荐
资源详情
资源评论
收起资源包目录
二阶锁相环Matlab程序及其FPGA程序 (480个子文件)
elaborate.bat 653B
compile.bat 497B
simulate.bat 386B
runme.bat 229B
runme.bat 229B
runme.bat 229B
TwoOderPll_tb_behav_6524_1499242774.btree 1.09MB
tb_FIRLpf.c 8KB
FIRLpfInt.coe 261B
FIRLpfInt.coe 261B
FIRLpfInt.coe 261B
FIRLpfInt.coe 261B
FIRLpfInt.coe 261B
FIRLpfInt.coe 261B
FIRLpfInt.coe 261B
FIRLpfInt.coe 261B
xsim.dbg 15KB
FIRLpf.dcp 607KB
FIRLpf.dcp 607KB
DDS.dcp 72KB
DDS.dcp 72KB
Mult8x8.dcp 44KB
Mult8x8.dcp 44KB
compile.do 2KB
compile.do 2KB
compile.do 1KB
compile.do 1KB
compile.do 847B
compile.do 831B
simulate.do 456B
simulate.do 334B
elaborate.do 328B
simulate.do 311B
elaborate.do 206B
simulate.do 191B
simulate.do 189B
elaborate.do 183B
simulate.do 183B
simulate.do 158B
simulate.do 158B
simulate.do 158B
wave.do 12B
wave.do 12B
wave.do 12B
wave.do 12B
wave.do 12B
wave.do 12B
simulate.do 11B
simulate.do 11B
simulate.do 11B
二阶环路设计.docx 339KB
~$二阶环路设计.docx 162B
xsimk.exe 723KB
filelist_irun.f 2KB
filelist.f 1KB
filelist.f 1KB
filelist.f 1KB
filelist.f 1KB
filelist.f 1KB
filelist_irun.f 786B
filelist_irun.f 537B
filelist.f 523B
filelist.f 523B
filelist.f 523B
filelist.f 523B
filelist.f 523B
filelist.f 335B
filelist.f 335B
filelist.f 335B
filelist.f 335B
filelist.f 335B
FIRLpf.h 4KB
FIRLpf.h 4KB
FIRLpf.h 4KB
FIRLpf.h 4KB
FIRLpf.h 4KB
FIRLpf.h 4KB
FIRLpf.h 4KB
usage_statistics_ext_xsim.html 4KB
usage_statistics_ext_labtool.html 3KB
.xsim_webtallk.info 59B
.xsim_webtallk.info 55B
webtalk.jou 937B
vivado.jou 760B
vivado.jou 752B
vivado.jou 732B
ISEWrap.js 7KB
ISEWrap.js 7KB
ISEWrap.js 7KB
rundef.js 1KB
rundef.js 1KB
rundef.js 1KB
runme.log 115KB
runme.log 63KB
runme.log 46KB
elaborate.log 17KB
compile.log 10KB
xvhdl.log 9KB
webtalk.log 1006B
xvlog.log 996B
共 480 条
- 1
- 2
- 3
- 4
- 5
资源评论
- weixin_382964132020-05-20程序运行没问题,不过有个小问题想问一下。 VIVADO程序里的assign carrier = 32'd171798691为什么可以表示400Hz啊。 为什么不是assign carrier = 32'd400呢?三百钱2021-04-24这个是频率控制字不是频率值,了解下DDS原理就会理解了。
- lengmian10012018-03-02相当不错,读了很多杜勇老师的著作,一次比一次好
- dalaodaidaiwo2018-01-11下载下来的是个链接,很奇怪,评论了再下载一次看看
- ninjacat032018-01-03试着跑了一下没问题,资源不错
三百钱
- 粉丝: 4
- 资源: 11
上传资源 快速赚钱
- 我的内容管理 展开
- 我的资源 快来上传第一个资源
- 我的收益 登录查看自己的收益
- 我的积分 登录查看自己的积分
- 我的C币 登录后查看C币余额
- 我的收藏
- 我的下载
- 下载帮助
最新资源
- 老飞飞搭建基础通用数据库V19数据库.rar
- jquery.js
- 机械设计多工位ACF贴胶带&预压设备sw18可编辑非常好的设计图纸100%好用.zip
- 基于Pytorch复现Point-Transformer,用于ShapeNet数据集点云分割
- 【医学影像分析】2D超声图像的分割检测(Ultrasound Nerve Segmentation - Kaggle数据集)
- 嘎嘎香的五款神仙谷歌插件
- .arch书源导入教程.mp4
- 贪心算法介绍及代码示例讲解
- CR13SP35MSI64 Crystal 水晶报表运行组件最后版本64位
- 图像分类数据集:玉米叶是否感染分类数据集(2分类,包含训练集、验证集)
资源上传下载、课程学习等过程中有任何疑问或建议,欢迎提出宝贵意见哦~我们会及时处理!
点击此处反馈
安全验证
文档复制为VIP权益,开通VIP直接复制
信息提交成功