system verilog验证实例

SYSDFV---Verification Example

第 1 页 /共 63 页

Verification with SystemVerilog

Verification Of Memory

In this example, we verify a simple single port RAM. Of course in real life

we really don't get to verify a memory model.

As usual our testbench will look as shown in figure below.

 Scoreboard

 SV testbench top

 Ports File

 HDL Testbench top

So the verification components are split into following blocks

1 `ifndef MEM_BASE_OBJECT_SV

2 `define MEM_BASE_OBJECT_SV

9 `endif

SYSDFV---Verification Example

第 2 页 /共 63 页

1 `ifndef MEM_TXGEN_SV

2 `define MEM_TXGEN_SV

3 class mem_txgen;

7 integer num_cmds;

9 function new(virtual mem_ports ports);

10 begin

11 num_cmds = 3;

18 begin

20 for (i=0; i < num_cmds; i ++ ) begin

21 mem_object = new();

22 mem_object.addr = $random();

23 mem_object.data = $random();

24 mem_object.rd_wr = 1;

26 mem_object.rd_wr = 0;

28 end

1 `ifndef MEM_DRIVER_SV

2 `define MEM_DRIVER_SV

4 class mem_driver;

5 virtual mem_ports ports;

7 function new(virtual mem_ports ports);

SYSDFV---Verification Example

第 3 页 /共 63 页

8 begin

9 this.ports = ports;

10 ports.address = 0;

11 ports.chip_en = 0;

12 ports.read_write = 0;

13 ports.data_in = 0;

14 end

15 endfunction

17 task drive_mem (mem_base_object object);

18 begin

19 @ (posedge ports.clock);

20 ports.address = object.addr;

28 $display("Driver : Memory read access-> Address : %x\n",

30 end

31 @ (posedge ports.clock);

32 ports.address = 0;

33 ports.chip_en = 0;

34 ports.read_write = 0;

35 ports.data_in = 0;

36 end

1 `ifndef MEM_IP_MONITOR_SV

2 `define MEM_IP_MONITOR_SV

3 class mem_ip_monitor;

6 virtual mem_ports ports;

SYSDFV---Verification Example

第 4 页 /共 63 页

8 function new (mem_scoreboard sb,virtual mem_ports ports);

9 begin

10 this.sb = sb;

11 this.ports = ports;

12 end

13 endfunction

16 task input_monitor();

17 begin

18 while (1) begin

19 @ (posedge ports.clock);

20 if ((ports.chip_en == 1) && (ports.read_write == 1)) begin

28 end

29 end

30 endtask

32 endclass

34 `endif

9 function new (mem_scoreboard sb,virtual mem_ports ports);

10 begin

11 this.sb = sb;

12 this.ports = ports;

13 end

14 endfunction

SYSDFV---Verification Example

第 5 页 /共 63 页

17 task output_monitor();

18 begin

19 while (1) begin

20 @ (negedge ports.clock);

21 if ((ports.chip_en == 1) && (ports.read_write == 0)) begin

22 mem_object = new();

23 $display("Output_monitor : Memory rd access->

Address : %x Data : %x",

25 mem_object.addr = ports.address;

26 mem_object.data = ports.data_out;

36 `endif

1 `ifndef MEM_SCOREBOARD_SV

2 `define MEM_SCOREBOARD_SV

4 class mem_scoreboard;

5 // Create a keyed list to store the written data

13 mem_object[input_object.addr] = input_object;

14 end

15 endtask

16 // post_output method is used by the output monitor to

17 // compare the output of memory with expected data

18 task post_output (mem_base_object output_object);

19 begin