module counter16(clk,clr,x,z,qout);
input clk,clr,x;
output reg z;
output reg [3:0]qout;
parameter
s0=4'b0000,s1=4'b0001,s2=4'b0010,s3=4'b0011,s4=4'b0100,s5=4'b0101,s6=4'b0110,s7=4'b0111,
s8=4'b1000,s9=4'b1001,s10=4'b1010,s11=4'b1011,s12=4'b1100,s13=4'b1101,s14=4'b1110,s15=4
'b1111;
always@(posedge clk or posedge clr)
begin
if(clr)
begin
qout<=s0;
z<=0;
end
else
begin
case(qout)
s0:
begin
if(x==0)
begin
qout<=s0;
z<=0;
end
else
begin
qout<=s1;
z<=0;
end
end
s1:
begin
if(x==0)
begin
qout<=s0;
z<=0;