没有合适的资源?快使用搜索试试~ 我知道了~
温馨提示
试读
90页
The Xilinx® LogiCORE™ IP AXI VDMA core is a soft IP core. It provides high-bandwidth direct memory access between memory and AXI4-Stream video type target peripherals including peripherals which support the AXI4-Stream Video protocol as described in the Video IP: AXI Feature Adoption section of the Vivado AXI Reference Guide (UG1037) [Ref 1].
资源推荐
资源详情
资源评论
AXI Video Direct
Memory Access v6.3
LogiCORE IP Product Guide
Vivado Design Suite
PG020 October 4, 2017
AXI VDMA v6.3 2
PG020 October 4, 2017 www.xilinx.com
Table of Contents
IP Facts
Chapter 1: Overview
Feature Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Unsupported Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Licensing and Ordering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Chapter 2: Product Specification
Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Resource Utilization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Port Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Register Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Genlock Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Chapter 3: Designing with the Core
General Design Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Clocking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Programming Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Chapter 4: Design Flow Steps
Customizing and Generating the Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Constraining the Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Synthesis and Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Chapter 5: Example Design
Implementing the Example Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Test Bench for the Example Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Simulating the Example Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Send Feedback
AXI VDMA v6.3 3
PG020 October 4, 2017 www.xilinx.com
Chapter 6: General Use Cases
Appendix A: Updating
Migrating to the Vivado Design Suite. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Upgrading in the Vivado Design Suite . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Appendix B: Debugging
Finding Help on Xilinx.com . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Vivado Design Suite Debug Feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Hardware Debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Appendix C: Frame Pointers Gray Code Outputs
Appendix D: Additional Resources and Legal Notices
Xilinx Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Documentation Navigator and Design Hubs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Please Read: Important Legal Notices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Send Feedback
AXI VDMA v6.3 4
PG020 October 4, 2017 www.xilinx.com Product Specification
Introduction
The Xilinx® LogiCORE™ IP AXI VDMA core is a
soft IP core. It provides high-bandwidth direct
memory access between memory and
AXI4-Stream video type target peripherals
including peripherals which support the
AXI4-Stream Video protocol as described in the
Video IP: AXI Feature Adoption section of the
Vivado AXI Reference Guide (UG1037)
[Ref 1].
Features
• AXI4 Compliant
• Primary AXI4 data width support of 32, 64,
128, 256, 512, and 1,024 bits
• Primary AXI4-Stream data width support of
multiples of 8 up to 1,024 bits
• Optional Data Realignment Engine
• Optional Genlock Synchronization
• Independent, asynchronous channel
operation
• Dynamic clock frequency change of
AXI4-Stream interface clocks
• Optional frame advance or repeat on error
• Supports up to 32 frame buffers
• Supports up to 64-bit address space
• Supports Vertical Flip
IP Facts
LogiCORE IP Facts Table
Core Specifics
Supported
Device
Family
(1)
UltraScale+™
UltraScale™
Zynq®-7000, 7 Series
Supported
User Interfaces
AXI4, AXI4-Lite, AXI4-Stream
Resources
Performance and Resource Utilization web
page
Provided with Core
Design Files
(2)
VHDL
Example
Design
Provided
Test Bench Provided
Constraints
File
Provided
Simulation
Model
Not Provided
Supported
S/W Drivers
(3)
Standalone and Linux
Tested Design Flows
(4)
Design Entry Vivado® Design Suite
Simulation
For supported simulators, see the
Xilinx Design Tools: Release Notes Guide.
Synthesis Vivado Synthesis
Support
Provided by Xilinx at the Xilinx Support web page
Notes:
1. For a complete list of supported devices, see the Vivado
IP catalog.
2. Contains a few Verilog files. Top level is VHDL.
3. Standalone driver information can be found in the
Software Developers Kit (SDK) installation directory. See
xilinx_drivers.htm in
<install_directory>/SDK/<release>/data/embeddedsw/
doc/xilinx_drivers.htm. Linux OS and driver support
information is available from the Xilinx Wiki page.
4. For the supported versions of the tools, see the
Xilinx Design Tools: Release Notes Guide.
Send Feedback
AXI VDMA v6.3 5
PG020 October 4, 2017 www.xilinx.com
Chapter 1
Overview
Many video applications require frame buffers to handle frame rate changes or changes to
the image dimensions (scaling or cropping). The AXI VDMA is designed to allow for efficient
high-bandwidth access between the AXI4-Stream video interface and the AXI4 interface.
Figure 1-1 illustrates the AXI VDMA Block Diagram.
After registers are programmed through the AXI4-Lite interface, the Control/ Status logic
block generates appropriate commands to the DataMover to initiate Write and Read
commands on the AXI4 Master interface.
A configurable asynchronous line buffer is used to temporarily hold the pixel data prior to
writing it out to the AXI4-Memory Map interface or the AXI4-Stream interface.
In the Write path, the AXI VDMA accepts frames on the AXI4-Stream Slave interface and
writes it to system memory using the AXI4 Master interface.
In the Read path, the AXI VDMA uses the AXI4 Master interface for reading frames from
system memory and outputs it on the AXI4-Stream Master interface.
Both write and read paths operate independently. The AXI VDMA also provides an option to
synchronize the incoming/outgoing frames with an external synchronization signal.
X-Ref Target - Figure 1-1
Figure 1‐1: AXI VDMA Block Diagram
AXI4-Lite
AXI4-Stream
Registers
DataMover Line Buffer
Control and
Status
X13213
AXI4 Memory Map
Send Feedback
剩余89页未读,继续阅读
资源评论
①只小码蚁
- 粉丝: 3
- 资源: 3
上传资源 快速赚钱
- 我的内容管理 展开
- 我的资源 快来上传第一个资源
- 我的收益 登录查看自己的收益
- 我的积分 登录查看自己的积分
- 我的C币 登录后查看C币余额
- 我的收藏
- 我的下载
- 下载帮助
最新资源
- JAVA 中的Spring框架介绍包括起源、体系结构、核心部分、特点等
- 2024年小米汽车产业链分析及新品上市全景洞察报告
- 基于Qt和C++实现的偏3D风格的异型窗体界面操作+源码(期末大作业&课设&项目开发)
- 基于yolov8的花卉分类系统,包含训练好的权重和推理代码,GUI界面,支持图片、视频、摄像头输入,支持检测结果导出
- 基于图形化编程的单片机教学案例研究
- 基于matlab语音识别的信号灯图像模拟控制技术代码19
- ET200SP-GSD文件-GSDML-V2.43-Siemens-ET200SP-20240209.zip
- STM32CubeIDE H743 + DP83848 + LWIP-UDP服务器跨网段传输数据
- 基于蓝牙单片机的锌烟除尘控制系统
- 基于matlab的hough变换道路提示牌检测识别系统代码18
资源上传下载、课程学习等过程中有任何疑问或建议,欢迎提出宝贵意见哦~我们会及时处理!
点击此处反馈
安全验证
文档复制为VIP权益,开通VIP直接复制
信息提交成功