TMS320F2810, TMS320F2811, TMS320F2812
TMS320C2810, TMS320C2811, TMS320C2812
Digital Signal Processors
Data Manual
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Literature Number: SPRS174L
April 2001 − Revised December 2004
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Revision History
3
April 2001 − Revised June 2004 SPRS174K
REVISION HISTORY
This data sheet revision history highlights the technical changes made to the SPRS174K device-specific data
sheet to make it an SPRS174L revision.
Global change: Added the ZHH package
PAGE
NO.
ADDITIONS/CHANGES/DELETIONS
15 Changed notes on Table 2−1
15 Added the ZHH package to Table 2−1 and changed the Product Status from TMX to TMS
16 Added the ZHH package to Section 2.3
19 Added a line to the description of XCLKOUT in Table 2−2
37 Added new Table 3−4, Boot Mode Selection
47 Modified the note on interrupts in Table 3−11
64 Modified the equation in section 4.3
75 Changed PCR1 to PCR in Table 4−7
85 Modified Figure 4−12 and changed title from “Modes of Operation” to “GPIO/Peripheral Pin Multiplexing”
87 Added ZHH package to Figure 5−1
87 Updated section 5.2, Documentation Support
92 Added a new row and two footnotes to the Electrical Characterisitcs Over Recommended Operating Conditions table
(section 6.3)
92 Added VDD1 to the first footnote of the Current Consumption by Power-Supply Pins Over Recommended Operating
Conditions During Low-Power Modes at 150-MHz SYSCLKOUT (TMS320F281x) table (section 6.4)
93 Added new values to the Current Consumption by Power-Suply Pins Over Recommended Operating Cnditions During
Low-Power Modes at 150-MHz SYSCLKOUT (TMS320C281x) (section 6.5)
94−95 Added Figure 6−1−through Figure 6−4
107 Added Table 6−10 as part of splitting IDLE mode timing requirements and switiching characteristics into two separate tables
107 Added Table 6−12 as part of splitting STANDBY mode timing requirements and switiching characteristics into two separate
tables
108 Added Table 6−14 as part of splitting HALT mode timing requirements and switiching characteristics into two separate tables
153 Added new Table 6−60 ROM Access Timing
153 Added new Table 6−61 Minimum Required Wait-States at Different Frequencies (C281x devices)
154 Added section 6.33 Migrating From F281x to C281x Devices
4
April 2001 − Revised June 2004SPRS174K
This page is intentionally left blank.
Contents
5
April 2001 − Revised December 2004 SPRS174L
Contents
Section Page
1 Features 13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2 Introduction 14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1 Description 14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2 Device Summary 15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3 Pin Assignments 16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3.1 Terminal Assignments for the GHH Package 16. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3.2 Pin Assignments for the PGF Package 17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3.3 Pin Assignments for the PBK Package 18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4 Signal Descriptions 19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3 Functional Overview 28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1 Memory Map 29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2 Brief Descriptions 34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.1 C28x CPU 34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.2 Memory Bus (Harvard Bus Architecture) 35. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.3 Peripheral Bus 35. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.4 Real-Time JTAG and Analysis 35. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.5 External Interface (XINTF) (2812 Only) 35. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.6 Flash (F281x Only) 36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.7 ROM (C281x Only) 36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.8 M0, M1 SARAMs 36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.9 L0, L1, H0 SARAMs 36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.10 Boot ROM 36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.11 Security 37. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.12 Peripheral Interrupt Expansion (PIE) Block 38. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.13 External Interrupts (XINT1, XINT2, XINT13, XNMI) 38. . . . . . . . . . . . . . . . . . . . . . .
3.2.14 Oscillator and PLL 38. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.15 Watchdog 38. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.16 Peripheral Clocking 38. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.17 Low-Power Modes 39. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.18 Peripheral Frames 0, 1, 2 (PFn) 39. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.19 General-Purpose Input/Output (GPIO) Multiplexer 39. . . . . . . . . . . . . . . . . . . . . . . .
3.2.20 32-Bit CPU-Timers (0, 1, 2) 39. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.21 Control Peripherals 40. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.22 Serial Port Peripherals 40. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3 Register Map 40. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4 Device Emulation Registers 43. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5 External Interface, XINTF (2812 Only) 43. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5.1 Timing Registers 45. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5.2 XREVISION Register 45. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.6 Interrupts 46. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.6.1 External Interrupts 49. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.7 System Control 50. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.8 OSC and PLL Block 52. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.8.1 Loss of Input Clock 53. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.9 PLL-Based Clock Module 53. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.10 External Reference Oscillator Clock Option 54. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.11 Watchdog Block 54. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
