3
VTI7064xxxxx
64MbitSerialSRAM
Vilsion Technology Inc.
Rev.0.1,1/2017
Symbol Signal Type SPI Mode QPI Mode
V
DD
Power Core Power Supply
V
SS
Ground Core Supply Ground
CE# Input
Chip select signal, Active Low. When CE# input isHigh, memory will be in
Standby state
CLK Input Clock Signal
SI/SIO[0] I/O Serial Input I/O[0]
SO/SIO[1] I/O Serial Output I/O[1]
SIO[3:2] I/O I/O[3:2]
1
I/O[3:2]
Note:1,Fast read Quad access and Quad Write access in SPI Mode use SIO[3:2].Recommend to pull down to GND if no use of SIO[3:2] in SPI
mode.
3. Power up initialization
All products include an on−chip voltage sensor used to start the self−initialization process. When V
DD
reaches a
stable level at or above minimum V
DD
, the device will require 150μs to complete its self−initialization process. From
the beginning of power ramp to the end of the 150μs period, CLK should remain LOW, CE# should remain HIGH
(track V
DD
within 200mV) and SI/SO/SIO[3:0] should remain LOW.
After the 150us period the device requires initialization command sequence as it’s shown in Figure 2, and then the
device is ready for normal operation.
Figure 1. Power-Up Initialization Timing
Figure 2. Reset command sequence for Device Initialization
