2.8 Exclusive accesses ................................................ ................................................ 2-68
2.9 Processor events .................................................. .................................................. 2-70
2.10 Quality of Service .................................................................................................... 2-71
2.11 Barriers .................................................................................................................... 2-78
2.12 DVM messages ................................................... ................................................... 2-79
2.13 PCIe integration ................................................... ................................................... 2-80
2.14 Error handling .......................................................................................................... 2-82
2.15 CCIX Port Aggregation groups ................................................................................ 2-99
2.16 System Address Map ............................................................................................ 2-100
2.17 RN SAM ........................................................ ........................................................ 2-101
2.18 CXRA SAM ............................................................................................................ 2-106
2.19 HN-F SAM ...................................................... ...................................................... 2-107
2.20 RN and HN-F SAM programming .................................... .................................... 2-113
2.21 RN and HN-F SAM r2 Support .............................................................................. 2-121
2.22 RN and HN-F SAM r3 Support .............................................................................. 2-124
2.23 HN-I SAM .............................................................................................................. 2-125
2.24 Cross chip routing and ID mapping ................................... ................................... 2-135
2.25 CMN-600 r3 128 RN-F support ...................................... ...................................... 2-141
2.26 GIC communication over AXI4 Stream ports ............................ ............................ 2-144
2.27 Clocking ........................................................ ........................................................ 2-145
2.28 Reset .......................................................... .......................................................... 2-151
2.29 Power and clock management .............................................................................. 2-152
2.30 RN entry to and exit from Snoop and DVM domains ...................... ...................... 2-163
2.31 Link layer ....................................................... ....................................................... 2-166
2.32 CML Symmetric Multi-Processor (SMP) Support .................................................. 2-168
2.33 CML CCIX Slave Agent (CXSA) Support .............................................................. 2-169
Chapter 3 Programmers Model
3.1 About the programmers model .............................................................................. 3-171
3.2 Register summary ................................................ ................................................ 3-173
3.3 Register descriptions .............................................. .............................................. 3-195
3.4 CMN-600 programming ........................................... ........................................... 3-1068
3.5 CML programming ............................................... ............................................... 3-1069
3.6 Support for RN-Fs compliant with CHI Issue A specification ............... ............... 3-1077
Chapter 4 SLC Memory System
4.1 About the SLC memory system ..................................... ..................................... 4-1080
4.2 Configurable options ............................................................................................ 4-1082
4.3 Basic operation .................................................................................................... 4-1083
4.4 Cache maintenance operations ..................................... ..................................... 4-1084
4.5 Cacheable and Non-cacheable exclusives .......................................................... 4-1085
4.6 TrustZone technology support ...................................... ...................................... 4-1086
4.7 Snoop connectivity and control ............................................................................ 4-1087
4.8 QoS features ................................................... ................................................... 4-1088
4.9 CMN-600 Hardware-based cache flush engine ......................... ......................... 4-1090
4.10 Data Source Handling ............................................ ............................................ 4-1092
4.11 Software configurable memory region locking .......................... .......................... 4-1093
4.12 Software-configurable On-Chip Memory .............................. .............................. 4-1095
4.13 CMO propagation from HN-F to SN-F/SBSX ........................... ........................... 4-1096
4.14 Source-based SLC cache partitioning ................................ ................................ 4-1097
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