SystemC 设计 MIPS CPU 源代码

#include "STDAFX.h" #include "ITEM_INCLUDE.h" const int RunningTime=1000; int sc_main(int i,char * argv[]) { sc_clock clk("clk",10); START_IF mips_START_IF("START_IF"); sc_signal<sc_uint<32> > START_IF_pc_in,START_IF_pc_out; sc_signal<bool> START_IF_isDelay; mips_START_IF.START_IF_pc_in(START_IF_pc_in); mips_START_IF.START_IF_pc_out(START_IF_pc_out); mips_START_IF.START_IF_isDelay(START_IF_isDelay); mips_START_IF.clk(clk); Instr_Memory mips_instr_memory("Instr_Memory"); mips_instr_memory.address(START_IF_pc_out); sc_signal<sc_uint<32> > IF_ID_instr_in; mips_instr_memory.instr(IF_ID_instr_in); adder_pc mips_adder_pc("adder_pc"); mips_adder_pc.adder_pc_in(START_IF_pc_out); sc_signal<sc_uint<32> > adder_pc_out; mips_adder_pc.adder_pc_out(adder_pc_out); IF_ID mips_IF_ID("IF_ID"); mips_IF_ID.IF_ID_instr_in(IF_ID_instr_in); mips_IF_ID.IF_ID_pc_in(adder_pc_out); mips_IF_ID.IF_ID_isDelay(START_IF_isDelay); mips_IF_ID.clk(clk); sc_signal<sc_uint<32> > IF_ID_pc_out,IF_ID_instr_out; sc_signal<sc_uint<5> > IF_ID_rs,IF_ID_rt,IF_ID_rd; sc_signal<sc_uint<16> > IF_ID_imm; sc_signal<sc_uint<32> > IF_ID_jump_address; mips_IF_ID.IF_ID_pc_out(IF_ID_pc_out); mips_IF_ID.IF_ID_instr_out(IF_ID_instr_out); mips_IF_ID.IF_ID_rs(IF_ID_rs); mips_IF_ID.IF_ID_rt(IF_ID_rt); mips_IF_ID.IF_ID_rd(IF_ID_rd); mips_IF_ID.IF_ID_imm(IF_ID_imm); mips_IF_ID.IF_ID_jump_address(IF_ID_jump_address); imm_extender mips_imm_se("imm_extender"); mips_imm_se.imm_in(IF_ID_imm); sc_signal<bool> isSE; mips_imm_se.isSE(isSE); sc_signal<sc_uint<32> > ID_EX_imm_in; mips_imm_se.imm_out(ID_EX_imm_in); Register_File mips_reg_file("Register_File"); mips_reg_file.clk(clk); mips_reg_file.read_regID1(IF_ID_rs); mips_reg_file.read_regID2(IF_ID_rt); sc_signal<sc_uint<32> > result1,result2; mips_reg_file.result1(result1); mips_reg_file.result2(result2); sc_signal<bool> MEM_WB_isRegWrite; sc_signal<sc_uint<5> > MEM_WB_Reg_address; sc_signal<sc_uint<32> > MEM_WB_Reg_data; mips_reg_file.write_enabled(MEM_WB_isRegWrite); mips_reg_file.write_reg_data(MEM_WB_Reg_data); mips_reg_file.write_regID(MEM_WB_Reg_address); sc_signal<sc_uint<32> > resulta,resultb; sc_signal<sc_uint<2> > forwarda,forwardb; sc_signal<sc_uint<32> > ALU_result; sc_signal<sc_uint<32> > EX_MEM_ALU_result_out; sc_signal<sc_uint<32> > mem_data_out; Mux_4x32 SelA("SelA"); SelA.A0(result1); sc_signal<sc_uint<32> > A1,A2,A3; SelA.A1(ALU_result); SelA.A2(EX_MEM_ALU_result_out); SelA.A3(mem_data_out); SelA.out(resulta); SelA.S(forwarda); Mux_4x32 SelB("SelB"); SelB.A0(result2); SelB.A1(ALU_result); SelB.A2(EX_MEM_ALU_result_out); SelB.A3(mem_data_out); SelB.out(resultb); SelB.S(forwardb); Equal mips_equal("Equal"); mips_equal.A(resulta); mips_equal.B(resultb); sc_signal<bool> isEqual; mips_equal.isEqual(isEqual); ID_EX mips_ID_EX("ID_EX"); mips_ID_EX.clk(clk); mips_ID_EX.ID_EX_imm_in(ID_EX_imm_in); mips_ID_EX.ID_EX_regdata1_in(resulta); mips_ID_EX.ID_EX_regdata2_in(resultb); sc_signal<sc_uint<32> > ID_EX_instr_out; sc_signal<sc_uint<32> > ID_EX_imm_out; sc_signal<sc_uint<6> > ID_EX_ALUC; sc_signal<bool> ID_EX_ALUA,ID_EX_ALUB; sc_signal<sc_uint<32> > ID_EX_regdata1_out; sc_signal<sc_uint<32> > ID_EX_regdata2_out; mips_ID_EX.ID_EX_instr_out(ID_EX_instr_out); mips_ID_EX.ID_EX_imm_out(ID_EX_imm_out); mips_ID_EX.ID_EX_ALUA(ID_EX_ALUA); mips_ID_EX.ID_EX_ALUB(ID_EX_ALUB); mips_ID_EX.ID_EX_ALUC(ID_EX_ALUC); mips_ID_EX.ID_EX_regdata1_out(ID_EX_regdata1_out); mips_ID_EX.ID_EX_regdata2_out(ID_EX_regdata2_out); sa mips_sa("sa"); mips_sa.sa_in(ID_EX_imm_out); sc_signal<sc_uint<32> > sa_imm_out; mips_sa.sa_out(sa_imm_out); Mux_2x32 mips_alua("mips_alua"); Mux_2x32 mips_alub("mips_alub"); sc_signal<sc_uint<32> > ALU_ALUA_in,ALU_ALUB_in; mips_alua.A0(ID_EX_regdata1_out); mips_alua.A1(sa_imm_out); mips_alua.S(ID_EX_ALUA); mips_alua.out(ALU_ALUA_in); mips_alub.A0(ID_EX_regdata2_out); mips_alub.A1(ID_EX_imm_out); mips_alub.S(ID_EX_ALUB); mips_alub.out(ALU_ALUB_in); ALU mips_alu("ALU"); mips_alu.A(ALU_ALUA_in); mips_alu.B(ALU_ALUB_in); mips_alu.ALUC(ID_EX_ALUC); mips_alu.R(ALU_result); EX_MEM mips_EX_MEM("EX_MEM"); mips_EX_MEM.clk(clk); mips_EX_MEM.EX_MEM_ALU_result_in(ALU_result); mips_EX_MEM.EX_MEM_instr_in(ID_EX_instr_out); mips_EX_MEM.EX_MEM_regdata2_in(ID_EX_regdata2_out); sc_signal<sc_uint<32> > EX_MEM_instr_out; sc_signal<bool> EX_MEM_MemRead,EX_MEM_MemWrite; sc_signal<sc_uint<32> > EX_MEM_regdata2_out; mips_EX_MEM.EX_MEM_instr_out(EX_MEM_instr_out); mips_EX_MEM.EX_MEM_ALU_result_out(EX_MEM_ALU_result_out); mips_EX_MEM.EX_MEM_MemRead(EX_MEM_MemRead); mips_EX_MEM.EX_MEM_MemWrite(EX_MEM_MemWrite); mips_EX_MEM.EX_MEM_regdata2_out(EX_MEM_regdata2_out); /* Data_Memory mips_data_memory("Data_Memory"); mips_data_memory.clk(clk); mips_data_memory.address(EX_MEM_ALU_result_out); mips_data_memory.MemRead(EX_MEM_MemRead); mips_data_memory.MemWrite(EX_MEM_MemWrite); mips_data_memory.write_data(EX_MEM_regdata2_out); mips_data_memory.data_out(mem_data_out); */ Cache mips_cache("Cache"); mips_cache.clk(clk); mips_cache.Cache_isRead(EX_MEM_MemRead); mips_cache.Cache_isWrite(EX_MEM_MemWrite); mips_cache.Cache_Mem_address(EX_MEM_ALU_result_out); mips_cache.Cache_Write_data(EX_MEM_regdata2_out); mips_cache.Cache_Mem_dataout(mem_data_out); MEM_WB mips_MEM_WB("MEM_WB"); mips_MEM_WB.clk(clk); mips_MEM_WB.MEM_WB_ALU_result_in(EX_MEM_ALU_result_out); mips_MEM_WB.MEM_WB_instr_in(EX_MEM_instr_out); mips_MEM_WB.MEM_WB_Memdata_in(mem_data_out); mips_MEM_WB.MEM_WB_isRegWrite(MEM_WB_isRegWrite); mips_MEM_WB.MEM_WB_Reg_address(MEM_WB_Reg_address); mips_MEM_WB.MEM_WB_Reg_data(MEM_WB_Reg_data); Control_Unit mips_con("Control_Unit"); mips_con.CON_ID_instr_in(IF_ID_instr_out); mips_con.CON_EXE_instr_in(ID_EX_instr_out); mips_con.CON_MEM_instr_in(EX_MEM_instr_out); mips_con.CON_isEqual(isEqual); mips_con.CON_isSE(isSE); //决定是否跳转 sc_signal<bool> CON_Branch; mips_con.CON_Branch(CON_Branch); //决定跳转地址 sc_signal<bool> CON_Branch_address; mips_con.CON_Branch_address(CON_Branch_address); sc_signal<sc_uint<32> > CON_instr_out; mips_con.CON_instr_out(CON_instr_out); mips_ID_EX.ID_EX_instr_in(CON_instr_out); mips_con.CON_ForwardA(forwarda); mips_con.CON_ForwardB(forwardb); mips_con.CON_isDelay(START_IF_isDelay); branch_pc mips_branch_pc("branch_pc"); mips_branch_pc.pc_in(IF_ID_pc_out); mips_branch_pc.offset(ID_EX_imm_in); sc_signal<sc_uint<32> > branch_address; mips_branch_pc.pc_out(branch_address); Mux_2x32 mips_branch_mux("mips_branch_mux"); mips_branch_mux.A0(branch_address); mips_branch_mux.A1(IF_ID_jump_address); mips_branch_mux.S(CON_Branch_address); sc_signal<sc_uint<32> > final_branch_address; mips_branch_mux.out(final_branch_address); Mux_2x32 mips_pc_mux("mips_pc_mux"); mips_pc_mux.A0(adder_pc_out); mips_pc_mux.A1(final_branch_address); mips_pc_mux.S(CON_Branch); mips_pc_mux.out(START_IF_pc_in); /* Cache mips_cache("Cache"); sc_signal<sc_uint<22> > Cache_Mem_address; sc_signal<bool> Cache_isWrite,Cache_isRead; sc_signal<sc_uint<32> > Cache_Write_data; sc_signal<sc_uint<32> > Cache_Mem_dataout; mips_cache.Cache_Mem_address(Cache_Mem_address); mips_cache.Cache_isWrite(Cache_isWrite); mips_cache.Cache_Write_data(Cache_Write_data); mips_cache.Cache_Mem_dataout(Cache_Mem_dataout); mips_cache.Cache_isRead(Cache_isRead); Cache_test mips_cache_test("Cache_test"); mips_cache_test.clk(clk); mips_cache_test.memaddress(Cache_M