JEDEC Standard No. 21C, Release 29 DDR4 SDRAM SO-DIMM Design Specification
Page 4.20.25-2 Revision 1.31
Table of Contents
1 Product Description .......................................................................................................... 5
2 Environmental Requirements........................................................................................... 6
3 Connector Pinout and Signal Description....................................................................... 7
3.1 DDR4 SO-DIMM Connector Pin Assignments .....................................................................................10
4 Power Details ................................................................................................................... 12
4.1 DIMM Voltage Requirements ................................................................................................................12
4.2 Rules for Power-Up Sequence..............................................................................................................13
4.3 Feed Through Voltage (VFT).................................................................................................................13
5 Component Details.......................................................................................................... 14
5.1 Component Types and Placement .......................................................................................................17
5.2 Decoupling Guidelines ..........................................................................................................................17
6 DIMM Design Details ....................................................................................................... 18
6.1 Signal Groups ........................................................................................................................................18
6.2 Explanation of Net Structure Diagrams ...............................................................................................18
6.3 General Net Structure Routing Rules ..................................................................................................19
6.3.1 Clock, Control, and Address/Command Groups ...........................................................19
6.3.2 Lead-in vs. Loaded Sections .........................................................................................20
6.3.3 Length/Delay Matching to SDRAM Devices..................................................................21
6.3.4 Velocity Compensation..................................................................................................21
6.3.5 Load/Delay Compensation ............................................................................................21
6.3.6 Data and Strobe Group .................................................................................................22
6.3.7 ALERT_n Wiring............................................................................................................22
6.3.8 Via Compensation .........................................................................................................23
6.3.9 Plane Referencing.........................................................................................................24
6.4 Rules for Higher Speed (2666 Mb/s or Higher)....................................................................................25
6.5 Address Mirroring..................................................................................................................................26
6.6 DIMM Routing Space Constraints ........................................................................................................27
6.7 DIMM Physical Requirements...............................................................................................................28
6.7.1 Via Size .........................................................................................................................28
6.7.2 Component Pad Sizes and Geometry...........................................................................28
6.7.3 DRAM Package Size.....................................................................................................28
6.7.4 Clock Termination .........................................................................................................28
6.7.5 ZQ Calibration Wiring ....................................................................................................28
6.7.6 DQ Stub Resistor ..........................................................................................................29
6.7.7 TEN Wiring ....................................................................................................................29
6.8 Reference Stackups...............................................................................................................................29
6.9 Impedance Targets ................................................................................................................................31
6.10 SPD Wiring and Placement ...................................................................................................................32
6.11 DQ Mapping to Support CRC................................................................................................................33
7 Serial Presence Detect Component Specification........................................................ 36
7.1 Serial Presence Detect Definition.........................................................................................................36
8 Product Label................................................................................................................... 38
8.1 DDR4 DIMM Label Format for DRAM-only module types...................................................................38
8.2 DDR4 DIMM Label Format for Hybrid module types...........................................................................43
9 JEDEC Process................................................................................................................ 50
Downloaded by James Zhang (pat12155@gmail.com) on Feb 11, 2020, 7:47 pm PST
Wistron
