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Media Platforms and Services Group
ADSP-BF533 Blackfin® Processor Anomaly list
for Revision(s) ADSP-BF533-0.1, ADSP-BF533-0.2, ADSP-BF533-0.3
Created Mon Dec 13 13:45:36 2004 (IM)
These anomalies represent the currently known differences between revisions of Blackfin devices
and the functionality specified in the Blackfin data sheets and User's Manual. A revision number
with the form "-x.x" is branded on all parts. The Implementation field bits 15-0 of the ADSP-
BF533 DSPID core MMR register can be used to differentiate the revisions as shown below.
REVISION DSPID<15:0>
0.1 0x0001
0.2 0x0002
0.3 0x0003
Index ID Anomaly Summary ADSP-BF533-
0.1
ADSP-BF533-
0.2
ADSP-BF533-
0.3
1 05000066 Internal voltage regulator
can't be modified via
register writes
x . .
2 05000067 Watchpoints (Hardware
Breakpoints) are not
supported
x x .
3 05000070 SDRAM PSSE bit cannot
be set again after
SDRAM Powerup
x . .
4 05000074 A multi issue instruction
with dsp32shiftimm in
slot1 and store of a P
register in slot 2 is not
supported
x x x
5 05000079 Writing FIO_DIR can
corrupt a programmable
flag's data
x . .
6 05000086 Timer Auto-Baud Mode
requires the UART clock
to be enabled.
x . .
7 05000088 Internal Clocking Modes
on SPORT0 not
supported
x . .
8 05000092 Internal voltage regulator
does not wake up from
an RTC wakeup
x . .
9 05000093 The IFLUSH instruction
must be preceded by a
CSYNC instruction
x . .
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