DW8051核Verilog源代码和Datasheet_designwarecores资源-CSDN文库

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DW8051

databook

datasheet

verilog

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DW8051_ALL.rar （5个子文件）

DW8051_applications.rar 470KB

DW8051_verilog.rar 66KB

DW8051.txt 315B

dw8051.pdf 331KB

DW8051_databook.rar 701KB

DesignWare Library

DW8051 MacroCell

Data Sheet

Overview

The DesignWare

DW8051

™

MacroCell is a high-performance, configurable, fully synthesizable 8051 core that is binary compatible with

the industry standard 803x/805x microcontrollers. The DW8051 core is technology-independent and has been fabricated in both ASIC

and FPGA technologies. Designed for ease of use, the DW8051 includes the coreConsultant

™

tool, a user-friendly wizard, which guides

users through configuration, simulation and synthesis.

The DesignWare DW8051 MacroCell solution includes the DW8051 MacroCell, a reference design, and Synopsys’ extensive verification

environment. The high-performance architecture of the DW8051 provides up to three times performance improvement over the standard

8051 when operating at the same clock rate.

roven Quality

, Complete Solution

To ensure quality, the DW8051 was

developed accor

ding to Synopsys’ strict

design-for-reuse methodology. It has

under

gone extensive testing during the

design process and has been proven in

many different technologies. It has also

been tested with a variety of third-party

8051 development tools and 8051

evaluation boar

ds.

The DW8051’s high-performance, config-

urable, synthesizable ar

chitectur

e, combined

with the development environment, provides

a total solution for building low-cost, high-

per

for

mance embedded control systems

for a wide range of applications.

utomated Design Flow with Synopsys

coreConsultant

The DW80

51 MacroCell solution includes

the Synopsys coreConsultant tool, which

ovides the following ser

vices:

Activity checklist that guides users

through DW8051 design activities in

the correct order

Automatic, error-free DW8051

configuration,

including parameter

oss-dependency checking

Automatic configuration and operation

of the DW8051 verification environment

Automatic, high-quality synthesis with

users’ technology library and installed

version of Design Compiler

™

Automatic design checking and synthesis

results analysis

DW8051

sfr_data_in

mem_data_in

mem_ea_n

iram_data_out

irom_data_out

int0_n

int1_n

int2

int3_n

int4

int5_n

pfi

wdti

t2ex

rxd0_in

rxd1_in

test_mode_n

rst_in_n

por_n

clk

sfr_addr

sfr_data_out

sfr_wr

str_rd

mem_addr

mem_data_out

mem_wr_n

mem_rd_n

mem_pswr_n

mem_psrd_n

mem_ale

iram_addr

iram_data_in

iram_rd_n

iram_we1_in

iram_we2_n

irom_addr

irom_rd_n

irom_cs_n

port_pin_reg_n

p0_mem_reg_n

p0_addr_data_n

p2_mem_reg_n

txd0

rxd0_out

txd1

rxd1_out

t0_out

t1_out

t2_out

stop_mode_n

idle_mode_n

rst_out_n

DW8

051 Input/Output Signals

Users can operate coreConsultant in its GUI

mode (Figure 1) or in batch mode through its

command line interface.

Technical Advantages of the DW8051

4 clocks/instruction cycle versus 12 in

standard 8051

- Up to three times faster execution on

average versus standard 8051

Stretch memory cycle

- Allows application software to adjust to

different external RAM speeds

- MOVX in as little as eight clock cycles

Dual data pointers

- Impr

oves efficiency when moving large

blocks of data

Internal/external peripheral interface

- Special function register (SFR) bus in

DW8051 supports both internal and

external peripherals vs. internal only in

standar

d 80

Two optional full-duplex serial ports

Seven additional inter

rupts

SFR bus for adding custom peripherals

803x/805x Compatibility

The DW80

1 is compatible with the

standard 8051 instruction set and can be

configured to a wide range of industry

standar

d 803x/805x ar

chitectur

es. Control

signals for standard 803x/805x I/O ports are

included. Optional full-duplex serial ports and

third timer are selectable through parameters.

High-Performance Architecture

The DW8051 is a fully static and synchronous

design. Eliminating wasted bus cycles and

providing dual data pointers for moving large

data blocks achieve greater efficiency and

performance. The DW8051 MacroCell

typically contains ~10k-13k gates, depending

on the configuration and technology in which

it is implemented. It runs at greater than 300

megahertz in 90-nm process technology.

Lower performance applications also benefit

by being able to run at lower clock rates to

get the same performance as a standard 12

clocks/instr

uction 8051. Lower clock rates

lead to lower power consumption and lower

electro-magnetic interference (EMI).

dding Custom Designed P

eripherals

A typical 8051 allows peripheral interface

only thr

ough port logic. In addition to the

ports, the DW8051 also provides direct

access to peripherals through the memory

and SFR buses (Figure 2).

Users can interface additional peripherals

dir

ectly to the DW80

1’s memory bus.

This method allows them to make use of

the “str

etch” memory cycle feature to

interface slow peripherals.

Users can also directly attach custom

designed peripherals to the efficient SFR

bus, the same bus used for interfacing the

standard DW8051 internal peripherals.

SFR addresses that are not used for the

DW8051 internal SFRs are available for

connecting external peripherals. Adding

peripherals to the SFR bus offers the

following advantages:

- Faster read, write accesses; 1 clock

vs. 2 clocks using mem_bus

- Dir

ect addressing

- Takes advantage of bit

manipulation instructions

- Ef

ficient, compact code

Third-Party Development Tools Support

Synopsys has an active pr

ogram in place

to support third-party tools. Many industry

standard compilers, assemblers, ROM

monitors, and in-circuit emulators have been

tested for compatibility with the DW8051.

This allows integration of these tools into a

design envir

onment and pr

ovides a complete

development solution for DW80

1-based

embedded systems on a chip. Nohau

Corporation and Hitex Development Tools

provide in-circuit emulation support.

DW8

051

mem_bus

sfr_bus

peripheral peripheral

Figure 1. Example coreConsultant dialogs for DW8

051

Figure 2. DW8

051 external SFR and memory bus

评论收藏

内容反馈

u012666

2015-12-08

下了两次，文件破损，里面PDF可见，没有代码，不好意思，三颗星。
tsoc20052000

2012-10-09

很全面的资源。dw8051,verilog。感谢提供~
小懒_

2012-07-25

虽然不是8051指令集的标准文档，但是还是有帮助的。
殊语

2014-05-28

非常感谢分享，可以编译，还没看懂
「已注销」

2012-11-22

很全面，但里面的代码好像是比较久之前写的。可能有些落伍了。

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myfingerhurt

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