module tugedafinal(din,clk,adcclk,dout,dcadc,dcmdc1,dcmdc2,dcmdc3,dcmdc4,dcmdc5,dcmdc6,dcmdc7,dcmdc8,dcmdc9);
input din;
input clk;
output reg adcclk;
output reg dout;
output reg dcadc;
output reg dcmdc1;
output reg dcmdc2;
output reg dcmdc3;
output reg dcmdc4;
output reg dcmdc5;
output reg dcmdc6;
output reg dcmdc7;
output reg dcmdc8;
output reg dcmdc9;
reg con;
reg condin;
reg insclk;
reg [3:0] antenna;
reg [3:0] sample;
reg [7:0] con_count;
reg [7:0] adc_count;
reg [7:0] mdc_count;
reg [7:0] indata_buf;
reg [13:0] ins_count;
always@(posedge clk)
case(adc_count)
0:begin
adc_count<=adc_count+1;
adcclk<=1'b0;
end
80:begin
adc_count<=adc_count+1;
adcclk<=1'b1;
end
159:adc_count<=0;
default:adc_count<=adc_count+1;
endcase
always@(posedge insclk)
case(con_count)
0:begin
con<=1'b0;con_count<=con_count+1;end
15:begin
con<=1'b1;con_count<=con_count+1;end
24:begin
con<=1'b0;
con_count<=0;
end
default:con_count<=con_count+1;
endcase
always@(posedge adcclk)
case(ins_count)
0:begin
dout<=1'b1;
dcadc<=1'b1;
insclk<=1'b0;
if(sample==0)sample<=1;
