Digital system test and testable design

这是一本关于数字电路的测试以及可测性的书，其中测试部分用设计语言描述出来。这本书展示了如何采用一些已建立的RTL级设计来测试数字电路。本书主要采用Verilog HDL模型建立测试，具有较好的实践性。 This is a book on test and testability of digital circuits in which test is spoken in the language of design. In this book, the concepts of testing and testability are treated together with digital design practices and methodologies. We show how testing digital circuits designing testable circuits can take advantage of some of the well-established RT-level design and verification methodologies and tools. The book uses Verilog models and testbenches for implementing and explaining fault simulation and test generation algorithms. In the testability part, it describes various scan and BIST methods in Verilog and uses Verilog testbenches as virtual testers to examine and evaluate these testability methods. In designing testable circuits, we use Verilog testbenches to evaluate, and thus improve testability of a design.