module clock_top(clk,key,dig,seg);
input clk;
input[2:0] key;
output[7:0] dig;
output[7:0] seg;
reg[7:0] dig_r;
reg[7:0] seg_r;
reg[3:0] disp;
reg[24:0] count;
reg[23:0] hour;
reg[1:0] keynum;
reg sec,keyen;
reg[2:0] dout1,dout2,dout3;
wire[2:0] key_done;
assign dig=dig_r;
assign seg=seg_r;
/******************************/
always@(posedge clk)
begin
case(count[17:15])
3'd0:dig_r=8'b11111110;
3'd1:dig_r=8'b11111101;
3'd2:dig_r=8'b11111011;
3'd3:dig_r=8'b11110111;
3'd4:dig_r=8'b11101111;
3'd5:dig_r=8'b11011111;
3'd6:dig_r=8'b10111111;
3'd7:dig_r=8'b01111111;
endcase
case(count[17:15])
3'd0:disp=hour[3:0];
3'd1:disp=hour[7:4];
3'd2:disp=4'ha;
3'd3:disp=hour[11:8];
3'd4:disp=hour[15:12];
3'd5:disp=4'ha;
3'd6:disp=hour[19:16];
3'd7:disp=hour[23:20];
endcase
end
always@(posedge clk)
begin
case(disp)
4'h0:seg_r=8'hc0;
4'h1:seg_r=8'hf9;
4'h2:seg_r=8'ha4;
4'h3:seg_r=8'hb0;
4'h4:seg_r=8'h99;
4'h5:seg_r=8'h92;
4'h6:seg_r=8'h82;
4'h7:seg_r=8'hf8;
4'h8:seg_r=8'h80;
4'h9:seg_r=8'h90;
4'ha:seg_r=8'hbf;
default:seg_r=8'hff;
endcase
if((count[17:15]==3'd2)&&sec)
seg_r=8'hff;
else if((count[17:15]==3'd5)&&sec)
seg_r=8'hff;