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This document contains detailed information on power considerations, DC/AC electrical

characteristics, and AC timing speciﬁcations for .25

m (HiP4) devices in the

PowerQUICC II™ MPC8260 communications processor family. These devices include the

MPC8260, the MPC8255, the MPC8264, the MPC8265, and the MPC8266. Throughout this

document, these devices are collectively referred to as the MPC826xA.

The following topics are addressed:

Topic Page

Section 1.1, “Features” 2

Section 1.2, “Electrical and Thermal Characteristics” 6

Section 1.2.1, “DC Electrical Characteristics” 7

Section 1.2.2, “Thermal Characteristics” 11

Section 1.2.3, “Power Considerations” 11

Section 1.2.4, “AC Electrical Characteristics” 12

Section 1.3, “Clock Conﬁguration Modes” 20

Section 1.3.1, “Local Bus Mode” 20

Section 1.3.2, “PCI Mode” 23

Section 1.4, “Pinout” 29

Section 1.5, “Package Description” 43

Section 1.6, “Ordering Information” 45

NOTE: Document Revision History

Changes to this document are summarized in Table 22 on

page 45.

Technical Data

MPC8260AEC/D

Rev. 0.9 8/2003

MPC826xA (HiP4) Family

Hardware Speciﬁcations

MOTOROLA

MPC826xA (HiP4) Family Hardware Speciﬁcations

Features

— High-performance (6.6–7.65 SPEC95 benchmark at 300 MHz; 1.68 MIPs/MHz without

inlining and 1.90 Dhrystones MIPS/MHz with

— Supports bus snooping for data cache coherency

— Floating-point unit (FPU)

• Separate power supply for internal logic and for I/O

• Separate PLLs for G2 core and for the CPM

— G2 core and CPM can run at different frequencies for power/performance optimization

— Internal core/bus clock multiplier that provides 1.5:1, 2:1, 2.5:1, 3:1, 3.5:1, 4:1, 5:1, 6:1 ratios

— Internal CPM/bus clock multiplier that provides 2:1, 2.5:1, 3:1, 3.5:1, 4:1, 5:1, 6:1 ratios

• 64-bit data and 32-bit address 60x bus

— Bus supports multiple master designs

— Supports single- and four-beat burst transfers

— 64-, 32-, 16-, and 8-bit port sizes controlled by on-chip memory controller

— Supports data parity or ECC and address parity

• 32-bit data and 18-bit address local bus

— Single-master bus, supports external slaves

— Eight-beat burst transfers

— 32-, 16-, and 8-bit port sizes controlled by on-chip memory controller

• 60x-to-PCI bridge (MPC8265 and MPC8266 only)

— Programmable host bridge and agent

— 32-bit data bus, 66 MHz, 3.3 V

— Synchronous and asynchronous 60x and PCI clock modes

— All internal address space available to external PCI host

— DMA for memory block transfers

— PCI-to-60x address remapping

• System interface unit (SIU)

— Clock synthesizer

— Reset controller

— Real-time clock (RTC) register

— Periodic interrupt timer

— Hardware bus monitor and software watchdog timer

— IEEE 1149.1 JTAG test access port

• Twelve-bank memory controller

— Glueless interface to SRAM, page mode SDRAM, DRAM, EPROM, Flash and other user-

deﬁnable peripherals

— Byte write enables and selectable parity generation

— 32-bit address decodes with programmable bank size

— Three user programmable machines, general-purpose chip-select machine, and page-mode

pipeline SDRAM machine

— Byte selects for 64 bus width (60x) and byte selects for 32 bus width (local)

MPC826xA (HiP4) Family Hardware Speciﬁcations

MOTOROLA

Features

— Dedicated interface logic for SDRAM

• CPU core can be disabled and the device can be used in slave mode to an external core

• Communications processor module (CPM)

— Embedded 32-bit communications processor (CP) uses a RISC architecture for ﬂexible

support for communications protocols

— Interfaces to G2 core through on-chip 32-Kbyte dual-port RAM and DMA controller

— Serial DMA channels for receive and transmit on all serial channels

— Parallel I/O registers with open-drain and interrupt capability

— Virtual DMA functionality executing memory-to-memory and memory-to-I/O transfers

— Three fast communications controllers supporting the following protocols (only FCC1 and

FCC2 on the MPC8255):

– 10/100-Mbit Ethernet/IEEE 802.3 CDMA/CS interface through media independent

interface (MII)

– ATM—Full-duplex SAR protocols at 155 Mbps, through UTOPIA interface, AAL5,

AAL1, AAL0 protocols, TM 4.0 CBR, VBR, UBR, ABR trafﬁc types, up to 16 K external

connections

– Transparent

– HDLC—Up to T3 rates (clear channel)

— Two multichannel controllers (MCCs) (only MCC2 on the MPC8255)

– Each MCC handles 128 serial, full-duplex, 64-Kbps data channels.Each MCC can be split

into four subgroups of 32 channels each.

– Almost any combination of subgroups can be multiplexed to single or multiple TDM

interfaces up to four TDM interfaces per MCC

— Four serial communications controllers (SCCs) identical to those on the MPC860, supporting

the digital portions of the following protocols:

– Ethernet/IEEE 802.3 CDMA/CS

– HDLC/SDLC and HDLC bus

– Universal asynchronous receiver transmitter (UART)

– Synchronous UART

– Binary synchronous (BISYNC) communications

– Transparent

— Two serial management controllers (SMCs), identical to those of the MPC860

– Provide management for BRI devices as general circuit interface (GCI) controllers in time-

division-multiplexed (TDM) channels

– Transparent

– UART (low-speed operation)

— One serial peripheral interface identical to the MPC860 SPI

— One inter-integrated circuit (I

C) controller (identical to the MPC860 I

C controller)

– Microwire compatible

– Multiple-master, single-master, and slave modes

— Up to eight TDM interfaces (four on the MPC8255)

MOTOROLA

MPC826xA (HiP4) Family Hardware Speciﬁcations

Features

– Supports two groups of four TDM channels for a total of eight TDMs

– 2,048 bytes of SI RAM

– Bit or byte resolution

– Independent transmit and receive routing, frame synchronization

– Supports T1, CEPT, T1/E1, T3/E3, pulse code modulation highway, ISDN basic rate, ISDN

primary rate, Motorola interchip digital link (IDL), general circuit interface (GCI), and

user-deﬁned TDM serial interfaces

— Eight independent baud rate generators and 20 input clock pins for supplying clocks to FCCs,

SCCs, SMCs, and serial channels

— Four independent 16-bit timers that can be interconnected as two 32-bit timers

Additional features of the MPC826xA family are as follows:

• CPM

— 32-Kbyte dual-port RAM

— Additional MCC host commands

— Eight transfer transmission convergence (TC) layers between the TDMs and FCC2 to support

inverse multiplexing for ATM capabilities (IMA) (MPC8264 and MPC8266 only)

• CPM multiplexing

— FCC2 can also be connected to the TC layer.

• TC layer (MPC8264 and MPC8266 only)

— Each of the 8 TDM channels is routed in hardware to a TC layer block

– Protocol-speciﬁc overhead bits may be discarded or routed to other controllers by the SI

– Performing ATM TC layer functions (according to ITU-T I.432)

– Transmit (Tx) updates

– Cell HEC generation

– Payload scrambling using self synchronizing scrambler (programmable by the user)

– Coset generation (programmable by the user)

– Cell rate by inserting idle/unassigned cells

– Receive (Rx) updates

– Cell delineation using bit by bit HEC checking and programmable ALPHA and DELTA

parameters for the delineation state machine

– Payload descrambling using self synchronizing scrambler (programmable by the user)

– Coset removing (programmable by the user)

– Filtering idle/unassigned cells (programmable by the user)

– Performing HEC error detection and single bit error correction (programmable by user)

– Generating loss of cell delineation status/interrupt (LOC/LCD)

— Operates with FCC2 (UTOPIA 8)

— Provides serial loop back mode

— Cell echo mode is provided

— Supports both FCC transmit modes

– External rate mode—Idle cells are generated by the FCC (microcode) to control data rate.

剩余47页未读，继续阅读

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2014-07-02

官方资料，可供参考。

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