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BCM53115.rar （42个子文件）

BCM53115

BCM53115_Cadence格式

BCM53115.brd 5.61MB

BCM53115.DSN 3.61MB

BCM53115M_2009.pdf 4.71MB

BCM53115M_2008.pdf 4.22MB

BCM53115_AD格式

History

0000000000E84BF2

PAGE5 Connector.~(2).SchDoc.Zip 1KB

BCM53115_Library.~(1).SchLib.Zip 156B

BCM53115.~(2).PcbDoc.Zip 1.18MB

PAGE2 Power.~(2).SchDoc.Zip 1KB

PAGE1 Block Diagram.~(1).SchDoc.Zip 162B

BCM53115_Library.~(2).SchLib.Zip 1KB

PAGE6 RJ45&SFP.~(1).SchDoc.Zip 152B

BCM53115.~(1).PcbDoc.Zip 1.18MB

PAGE6 RJ45&SFP.~(2).SchDoc.Zip 1KB

PAGE1 Block Diagram.~(2).SchDoc.Zip 1KB

PAGE7 CPU&POE Module.~(2).SchDoc.Zip 1KB

PAGE8 LED INDUCTOR.~(2).SchDoc.Zip 1KB

PAGE4 BCM53115_Power.~(2).SchDoc.Zip 1KB

PAGE8 LED INDUCTOR.~(1).SchDoc.Zip 160B

BCM53115_Library.~(3).SchLib.Zip 429KB

BCM53115.~(1).PrjPcb.Zip 140B

PAGE5 Connector.~(1).SchDoc.Zip 154B

PAGE4 BCM53115_Power.~(1).SchDoc.Zip 164B

PAGE3 BCM53115_Ether Sw.~(2).SchDoc.Zip 1KB

BCM53115.~(2).PrjPcb.Zip 5KB

PAGE2 Power.~(1).SchDoc.Zip 146B

PAGE3 BCM53115_Ether Sw.~(1).SchDoc.Zip 170B

PAGE7 CPU&POE Module.~(1).SchDoc.Zip 166B

PAGE8 LED INDUCTOR.SchDoc 336KB

PAGE5 Connector.SchDoc 280KB

PSpice Models

PAGE6 RJ45&SFP.SchDoc 540KB

BCM53115.PcbDoc 7.52MB

PAGE7 CPU&POE Module.SchDoc 237KB

__Previews

PAGE1 Block Diagram.SchDocPreview 34KB

PAGE1 Block Diagram.SchDoc 151KB

PAGE2 Power.SchDoc 249KB

PAGE3 BCM53115_Ether Sw.SchDoc 478KB

BCM53115.PrjPcbStructure 897B

BCM53115_Library.SchLib 2.14MB

BCM53115.LOG 54KB

PAGE4 BCM53115_Power.SchDoc 767KB

BCM53115.PrjPcb 36KB

BCM53115_Layout.pdf 1018KB

8/11/2009 HLWCH

Data Sheet

BCM53115M

53115M-DS06-R

5300 California Avenue • Irvine, CA 92617 • Phone: 949-926-5000 • Fax: 949-926-5203 05/13/09

Multiport Gigabit Ethernet Switches

GENERAL DESCRIPTION

FEATURES

The Broadcom

BCM53115M is a highly integrated, cost-

effective smart-managed gigabit switch. The switch

design is based on the field-proven, industry-leading

ROBO architecture. This device combines all the

functions of a high-speed switch system including packet

buffers, PHY transceivers, media access controllers

(MACs), address management, port-based rate control,

and a non-blocking switch fabric into a single 65 nm

CMOS device. Designed to be fully compliant with the

IEEE 802.3 and IEEE 802.3x specifications, including the

MAC-control PAUSE frame, the BCM53115M provides

compatibility with all industry-standard Ethernet, Fast

Ethernet, and Gigabit Ethernet (GbE) devices.

The BCM53115M has a rich feature set suitable for not

only standard GbE connectivity for desktop and laptop

PCs, but also for next-generation gaming consoles, set-

top boxes, networked DVD players, and home theater

receivers. It is also specifically designed for next

generation SOHO/SMB routers and gateways.

The BCM53115M contains five full-duplex 10/100/1000

BASE-TX Ethernet transceivers. In addition, the

BCM53115M has one GMII/RGMII/MII/RvMII interface for

the CPU or a router chip, providing flexible

10/100/1000 Mbps connectivity. A GMII/RGMII/SGMII/

MII/RvMII interface for the WAN port can be configured as

an IMP port.

The BCM53115M provides 70+ on-chip MIB counters to

collect receive and transmit statistics for each port.

The BCM53115M is available in industrial temperature

(I-Temp) and commercial temperature (C-Temp) rated

packages. The industrial-grade BCM53115M is provided

in a 484-pin PBGA (23 mm x 23 mm) package. The

commercial-grade BCM53115M is provided in a 400-pin

FBGA (17 mm x 17 mm) package.

• Seven 10/100/1000 media access controllers

• Five-port 10/100/1000 transceivers for Tx

• One GMII/RGMII/MII/RvMII interface for an inband

management port (IMP) for connection to a CPU/

management entity without PHY

• One GMII/RGMII/SGMII/MII/RvMII interface for WAN

port

• Dual IMP ports support, WAN interface (Port 5) to be

IMP port-capable

• IEEE 802.1p, MAC Port, TOS, and DiffServ QoS for four

queues, plus two time sensitive queues

• Port-based VLAN

• IEEE 802.1Q-based VLAN with 4K entries

• MAC-based trunking with automatic link failover

• Port-based rate control

• Port mirroring

• Compact field processor (CFP)

-256 rules

- Filtering, classifications, remarking, and priority

actions

- Support IPv6

- Priority modification on egress

• BroadSync™ HD

- Timestamp tagging at MAC interface

- Time-aware egress scheduler

• DOS attack prevention

- Support IPv6

- Ingress mirroring

• IGMP Snooping, MLD snooping support

• Spanning tree support (multiple spanning trees–up to

eight)

• Loop detection for unmanaged configurations with

Broadcom’s patented LoopDTech™ technology

• CableChecker™ with unmanaged mode support

• Double tagging/QinQ

• Egress VID remarking

• IEEE802.3 as support

• IEEE 802.3x programmable per-port flow control and

backpressure, with IEEE 802.1x support for secure user

authentication

• EEPROM, MDC/MDIO, and SPI Interface.

• 4K entry MAC address table with automatic learning and

aging

• 128 KB packet buffer

• 128 multicast group support

• Jumbo frame support up to 9720 byte

• 1.2V for core and 3.3V for I/O

• JTAG support

• 484 PBGA

• 400 FBGA

8/11/2009 HLWCH

BCM53115M Data Sheet

05/13/09

Broadcom Corporation

Page ii Document 53115M-DS06-R

Figure 1: Functional Block Diagram

10/100/1000

PHY

BCM53115M

GMACTRD[3:0]_0 +/- (Port 0)

10/100/1000

PHY

GMACTRD[3:0]_1 +/- (Port 1)

10/100/1000

PHY

GMACTRD[3:0]_2 +/- (Port2)

10/100/1000

PHY

GMACTRD[3:0]_3 +/- (Port 3)

10/100/1000

PHY

GMACTRD[3:0]_4 +/- (Port 4)

GMAC

GMII/RGMII/MII/RvMII (IMP)

ContentAware™

Compact Field

Processor

Space

Packet Buffer

MMU

Address

Management

LED Interface

EEPROM

Interface

LED

EEPROM

GMII/RGMII/SGMII/MII/RvMII (Port 5)

GMAC

SGMII/SerDes

8/11/2009 HLWCH

Data Sheet BCM53115M

05/13/09

Broadcom Corporation

Document 53115M-DS06-R Page iii

REVISION HISTORY

Revision Date Change Description

53115M-DS06-R 05/13/09 Updated:

• Table 16, ”Behavior for Reserved Multicast Addresses,” on page 50

• Table 227, ”Default IEEE 802.1Q Tag Register (Page 34h: Address 10h–21h),” on

page 261

53115M-DS05-R 05/01/09 Updated:

• “Ethernet AV” to “BroadSync HD” globally

• “Double-Tagging” on page 10

• “VLAN Tagging Structure Parsing” on page 24

• Bits 7:2 R/W value in Table 45, ”Switch Mode Register (Page 00h: Address 0Bh),” on

page 139

• Bit 5 R/W value in Table 46, ”IMP Port State Override Register (Page 00h: Address

0Eh),” on page 139

• Bits 15:9 R/W value in Table 61, ”Multicast Lookup Failed Forward Map Register

(Page 00h: Address 34h–35h),” on page 147

• Table 72, ”Pause Frame Detection Control Register (Page 00h: Address 80h),” on

page 151

• Bits 13:6 R/W value in Table 90, ”Mirror Capture Control Register (Page 02h:

Address 10h–11h),” on page 159

• Bits 15:10 R/W value in Table 92, ”Ingress Mirror Divider Register (Page 02h:

Address 14h–15h),” on page 160

• Bits 15:10 R/W value in Table 95, ”Egress Mirror Divider Register (Page 02h:

Address 1Eh–1Fh),” on page 162

• R/W values in Table 101, ”Global ARL Configuration Register (Page 04h: Address

00h),” on page 166

• Bits 6:1 R/W value in Table 109, ”ARL Table Read/Write Control Register (Page 05h:

Address 00h),” on page 171

• 5Ch–5Fh ADDR value in Table 195, ”Page 20h–28h Port MIB Registers,” on page

237

• R/W values in Table 215, ”MAC Trunk Control Register (Page 32h: Address 00h),” on

page 252

• Bits 15:12 R/W value in Table 225, ”VLAN Multiport Address Control Register (Page

34h: Address 0Ah–0Bh),” on page 259

• Table 227, ”Default IEEE 802.1Q Tag Register (Page 34h: Address 10h–21h),” on

page 261

8/11/2009 HLWCH

BCM53115M Data Sheet

05/13/09

Broadcom Corporation

Page iv Document 53115M-DS06-R

53115M-DS05-R

(cont.)

05/01/09 Updated:

• Bits 5:0 Default in Table 242, ”Global Rate Control Register (Page 41h: Address

00h–03h),” on page 269

• Bits 7:0 in Table 246, ”Port Egress Rate Control Configuration Registers (Page 41h:

Address 80h–91h),” on page 274

• R/W values in Table 251, ”EAP Global Control Registers (Page 42h: Address 00h),”

on page 276

• Bits 7:6 R/W value in Table 252, ”EAP Multiport Address Control Register (Page 42h:

Address 01h),” on page 277

• Bit 14 R/W value in Table 284, ”BroadSync HD Class 5 Bandwidth Control Register

(Page 90h: Address 30h–31h, 32h–33h, 34h–35h, 36h–37h, 38h–39h),” on page

288

• Bits 15:14 R/W value in Table 286, ”BroadSync HD Class 4 Bandwidth Control

page 288

• Bits 15:5 R/W value in Table 290, ”BroadSync HD Link Status Register (Page 90h:

Address B0h–B1h),” on page 289

• Bits 31:25 R/W value in Table 292, ”Traffic Remarking Control Register (Page 91h:

Address 00h),” on page 290

53115M-DS04-R 12/17/08 Updated:

• LED MODE[1:0] in Table 35, ”Signal Type Definitions,” on page 112

• Table 43, ”Port Control Register (Page 00h: Address 00h–05h),” on page 139

• Bit 5 and 4 in Table 68, ”Port State Override Register (Page 00h: Address 58h–5Fh),”

on page 151

• Bits 5:4 in Table 90, ”Mirror Capture Control Register (Page 02h: Address 10h–11h),”

on page 160

53115M-DS03-R 11/21/08 Updated:

• Table 35, ”Signal Type Definitions,” on page 112.

• Section 12 ”Ordering Information” on page 333.

Added:

• Figure 78, ”BCM53115M Marking Information,” on page 332.

53115M-DS02-R 09/02/08 Updated:

• “IGMP Snooping” on page 19.

• “LED Interfaces” on page 106.

• Table 87 on page 159.

• Table 171 on page 218.

• Table 173 on page 220.

• Table 177 on page 223.

• Table 179 on page 226.

• Table 180 on page 228.

• Table 181 on page 229.

• Table 187 on page 234.

• Table 188 on page 235.

• Table 189 on page 235.

• Table 190 on page 236.

• Table 207 on page 249.

• Table 230 on page 263.

• Added new symbols to Table 328 on page 310.

• Table 329 on page 311.

Revision Date Change Description

8/11/2009 HLWCH

Data Sheet BCM53115M

05/13/09

Broadcom Corporation

Document 53115M-DS06-R Page v

53115M-DS01-R 01/25/08 Updated:

• Table 2, ”Reasons to Forward a Packet to the CPU,” on page 7

• “Search Key Composition” on page 33

• Slice_ID in Table 7, ”Slice N Key for IPv6 Packet,” on page 35, Table 8, ”Slice N Key

for Non-IP Packet,” on page 36, and Table 9, ”Chain Slice Key for IPv6 Packet,” on

page 37

• “CableChecker™” on page 45

• Figure 21, ”Address Table Organization,” on page 47

• Cross references in “MIB Engine” on page 69

• Table 35, ”Signal Type Definitions,” on page 112

• Table 48, ”LED Refresh Register (Page 00h: Address 0Fh),” on page 141

• Default values in Table 49, ”LED Function 0 Control Register (Page 00h: Address

10h–11h),” on page 142 and Table 50, ”LED Function 1 Control Register (Page 00h:

Address 12h–13h),” on page 143

• Table 51, ”LED Function Map Register (Page 00h: Address 14h–15h),” on page 143

• Table 52, ”LED Enable Map Register (Page 00h: Address 16h–17h),” on page 144

• Table 53, ”LED Mode Map 0 Register (Page 00h: Address 18h–19h),” on page 144

• Table 57, ”WAN Port Select Register (Page 00h: Address 26h–27h),” on page 146

• Table 126, ”Register Map (Page 10h–14h),” on page 180

• Bit 18 and bit 6 in Table 242, ”Global Rate Control Register (Page 41h: Address 00h–

03h),” on page 270

• Descriptions in Table 297, ”CFP TCAM Data Register 0 (Page A0h: Address 10h–

13h),” on page 296 through Table 312, ”CFP TCAM Mask Register 7 (Page A0h:

Address 4Ch–4Fh),” on page 299

• Pins in Table 326, ”Absolute Maximum Ratings,” on page 309 and Table 327,

”Recommended Operating Conditions,” on page 309

• Table 328, ”Electrical Characteristics,” on page 310

• Figure 61, ”MII Input Timing,” on page 312 and Table 330, ”MII Input Timing,” on page

312

• Figure 62, ”MII Output Timing,” on page 313 and Table 331, ”MII Output Timing,” on

page 313

• Figure 63, ”Reverse MII Input Timing,” on page 314 and Table 332, ”Reverse MII

Input Timing,” on page 314

• Figure 64, ”Reverse MII Output Timing,” on page 315 and Table 333, ”Reverse MII

Output Timing,” on page 315

• Table 338, ”GMII Output Timing,” on page 320

• Figure 70, ”GMII Input Timing,” on page 321 and Table 339, ”GMII Input Timing,” on

page 321

• Table 345, ”BCM53115MKFB Package—With Heat Sink,” on page 326

Added:

• Table 158, ”Interrupt Mask Register (Page 10h–14h: Address 36h),” on page 206

• Table 346, ”BCM53115MIPB Package—With Heat Sink,” on page 326

53115M-DS00-R 09/11/07 Initial release.

Revision Date Change Description

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