FM25V02铁电驱动程序_fm25v20资源-CSDN文库

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FM25V02

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LPC2387_Ferroelectric (v0.2).rar （73个子文件）

LPC2387_Ferroelectric (v0.2)

FM25V02铁电存储器数据手册pdf格式.pdf 166KB

LPC2387_Ferroelectric (v0.2)

spi0.crf 31KB

FM25V02铁电存储器数据手册pdf格式.pdf 166KB

pll

Pll.c 5KB

Pll.h 678B

spi0.d 147B

LPC2387_uvproj.bak 16KB

sdcmd.d 263B

pll.d 111B

LPC2387.uvgui.Administrator 69KB

uart.o 70KB

irq.d 91B

LPC2300.o 4KB

timer0.o 70KB

LPC2387.uvgui_qmjg.bak 138KB

irq.crf 30KB

main.crf 34KB

sdhal.o 94KB

uart.crf 34KB

ssp1.o 71KB

LPC2300.d 22B

SPI0

SPI0.h 1KB

SPI0.c 12KB

spp1.__i 264B

sddriver.d 296B

timer0.d 186B

ExtDll.iex 19B

sdhal.d 335B

ssp1.d 147B

LPC2387.axf 46KB

LPC2300.lst 97KB

LPC2387_uvopt.bak 12KB

uart

uart.h 1KB

uart.c 7KB

pll.o 69KB

main.d 275B

main

main.c 2KB

main.h 0B

Timer0

Timer0.h 105B

Timer0.c 4KB

spi0.o 72KB

LPC2387.sct 479B

irq.o 68KB

sdhal.crf 54KB

LPC2387.plg 238B

LPC2387.uvgui.qmjg 138KB

spp1.crf 28KB

hcj 2KB

sdcmd.crf 49KB

LPC2387.htm 62KB

LPC2387_Target 1.dep 3KB

uart.d 194B

LPC2300.s 36KB

sddriver.crf 49KB

main.o 74KB

spp1.d 51B

pll.crf 30KB

includes

LPC23xx.h 72KB

type.h 787B

includes.h 199B

LPC2387.map 132KB

sdcmd.o 90KB

LPC2387.uvgui_Administrator.bak 69KB

LPC2387.uvproj 16KB

timer0.crf 31KB

ssp1.crf 31KB

sddriver.o 89KB

JLinkArm_Target 1.ini 549B

irq

irq.c 3KB

irq.h 3KB

LPC2387.lnp 288B

LPC2387.tra 1KB

LPC2387.uvopt 12KB

Product Preview

This is a product under development. Device specifications are design Ramtron International Corporation

goals and are subject to change. Ramtron reserves the right to change 1850 Ramtron Drive, Colorado Springs, CO 80921

or discontinue this product without notice. (800) 545-FRAM, (719) 481-7000

Rev. 0.1

http://www.ramtron.com

Mar. 2009 Page 1 of 15

FM25V02

256Kb Serial 3V F-RAM Memory

Features

256K bit Ferroelectric Nonvolatile RAM

• Organized as 32K x 8 bits

• High Endurance 100 Trillion (10

) Read/Writes

• 10 Year Data Retention

• NoDelay™ Writes

• Advanced High-Reliability Ferroelectric Process

Very Fast Serial Peripheral Interface - SPI

• Up to 40 MHz Frequency

• Direct Hardware Replacement for Serial Flash

• SPI Mode 0 & 3 (CPOL, CPHA=0,0 & 1,1)

Write Protection Scheme

• Hardware Protection

• Software Protection

Device ID and Serial Number

• Device ID reads out Manufacturer ID & Part ID

• Unique Serial Number (FM25VN02)

Low Voltage, Low Power

• Low Voltage Operation 2.0V – 3.6V

• 90 µA Standby Current (typ.)

• 5 µA Sleep Mode Current (typ.)

Industry Standard Configurations

• Industrial Temperature -40°C to +85°C

• 8-pin “Green”/RoHS SOIC Package

Description

The FM25V02 is a 256-kilobit nonvolatile memory

employing an advanced ferroelectric process. A

ferroelectric random access memory or F-RAM is

nonvolatile and performs reads and writes like a

RAM. It provides reliable data retention for 10 years

while eliminating the complexities, overhead, and

system level reliability problems caused by Serial

Flash and other nonvolatile memories.

Unlike Serial Flash, the FM25V02 performs write

operations at bus speed. No write delays are incurred.

Data is written to the memory array immediately

after it has been transferred to the device. The next

bus cycle may commence without the need for data

polling. The product offers very high write

endurance, orders of magnitude more endurance than

Serial Flash. Also, F-RAM exhibits lower power

consumption than Serial Flash.

These capabilities make the FM25V02 ideal for

nonvolatile memory applications requiring frequent

or rapid writes or low power operation. Examples

range from data collection, where the number of

write cycles may be critical, to demanding industrial

controls where the long write time of Serial Flash can

cause data loss.

The FM25V02 provides substantial benefits to users

of Serial Flash as a hardware drop-in replacement.

The devices use the high-speed SPI bus, which

enhances the high-speed write capability of F-RAM

technology. The FM25VN02 is offered with a unique

serial number that is read-only and can be used to

identify a board or system. Both devices incorporate

a read-only Device ID that allows the host to

determine the manufacturer, product density, and

product revision. The devices are guaranteed over an

industrial temperature range of -40°C to +85°C.

Pin Configuration

VSS

VDD

HOLD

Pin Name Function

/S Chip Select

/W Write Protect

/HOLD Hold

C Serial Clock

D Serial Data Input

Q Serial Data Output

VDD Supply Voltage

VSS Ground

FM25V02 - 256Kb SPI FRAM

Rev. 0.1

Mar. 2009 Page 2 of 15

Instruction Decode

Clock Generator

Control Logic

Write Protect

Instruction Register

Address Register

Counter

4096 x 64

FRAM Array

Data I/O Register

Nonvolatile Status

HOLD

Figure 1. Block Diagram

Pin Descriptions

Pin Name I/O Description

/S Input Chip Select: This active-low input activates the device. When high, the device enters

low-power standby mode, ignores other inputs, and all outputs are tri-stated. When

low, the device internally activates the C signal. A falling edge on /S must occur prior

to every op-code.

C Input Serial Clock: All I/O activity is synchronized to the serial clock. Inputs are latched on

the rising edge and outputs occur on the falling edge. Since the device is static, the

clock frequency may be any value between 0 and 40 MHz and may be interrupted at

any time.

/HOLD Input Hold: The /HOLD pin is used when the host CPU must interrupt a memory operation

for another task. When /HOLD is low, the current operation is suspended. The device

ignores any transition on C or /S. All transitions on /HOLD must occur while C is low.

This pin has a weak internal pull-up (see R

spec, pg 11). However, if it is not used,

the /HOLD pin should be tied to V

/W Input Write Protect: This active-low pin prevents write operations to the Status Register

only. A complete explanation of write protection is provided on pages 6 and 7. If not

used, the /W pin should be tied to V

D Input Serial Input: All data is input to the device on this pin. The pin is sampled on the

rising edge of C and is ignored at other times. It should always be driven to a valid

logic level to meet I

specifications.

* D may be connected to Q for a single pin data interface.

Q Output Serial Output: This is the data output pin. It is driven during a read and remains tri-

stated at all other times including when /HOLD is low. Data transitions are driven on

the falling edge of the serial clock.

* Q may be connected to D for a single pin data interface.

VDD Supply Power Supply

VSS Supply Ground

FM25V02 - 256Kb SPI FRAM

Rev. 0.1

Mar. 2009 Page 3 of 15

Overview

The FM25V02 is a serial F-RAM memory. The

memory array is logically organized as 32,768 x 8

and is accessed using an industry standard Serial

Peripheral Interface or SPI bus. Functional operation

of the F-RAM is similar to Serial Flash. The major

differences between the FM25V02 and a Serial Flash

with the same pinout are the F-RAM’s superior write

performance, very high endurance, and lower power

consumption.

Memory Architecture

When accessing the FM25V02, the user addresses

32K locations of 8 data bits each. These data bits are

shifted serially. The addresses are accessed using the

SPI protocol, which includes a chip select (to permit

multiple devices on the bus), an op-code, and a two-

byte address. The complete address of 15-bits

specifies each byte address uniquely.

Most functions of the FM25V02 either are controlled

by the SPI interface or are handled automatically by

on-board circuitry. The access time for memory

operation is essentially zero, beyond the time needed

for the serial protocol. That is, the memory is read or

written at the speed of the SPI bus. Unlike Serial

Flash, it is not necessary to poll the device for a ready

condition since writes occur at bus speed. So, by the

time a new bus transaction can be shifted into the

device, a write operation will be complete. This is

explained in more detail in the interface section.

Users expect several obvious system benefits from

the FM25V02 due to its fast write cycle and high

endurance as compared to Serial Flash. In addition

there are less obvious benefits as well. For example

in a high noise environment, the fast-write operation

is less susceptible to corruption than Serial Flash

since it is completed quickly. By contrast, Serial

Flash requiring milliseconds to write is vulnerable to

noise during much of the cycle.

Serial Peripheral Interface – SPI Bus

The FM25V02 employs a Serial Peripheral Interface

(SPI) bus. It is specified to operate at speeds up to

40MHz. This high-speed serial bus provides high

performance serial communication to a host

microcontroller. Many common microcontrollers

have hardware SPI ports allowing a direct interface.

It is quite simple to emulate the port using ordinary

port pins for microcontrollers that do not. The

FM25V02 operates in SPI Mode 0 and 3.

Protocol Overview

The SPI interface is a synchronous serial interface

using clock and data pins. It is intended to support

multiple devices on the bus. Each device is activated

using a chip select. Once chip select is activated by

the bus master, the FM25V02 will begin monitoring

the clock and data lines. The relationship between the

falling edge of /S, the clock and data is dictated by

the SPI mode. The device will make a determination

of the SPI mode on the falling edge of each chip

select. While there are four such modes, the

FM25V02 supports only modes 0 and 3. Figure 2

shows the required signal relationships for modes 0

and 3. For both modes, data is clocked into the

FM25V02 on the rising edge of C and data is

expected on the first rising edge after /S goes active.

If the clock starts from a high state, it will fall prior to

the first data transfer in order to create the first rising

edge.

The SPI protocol is controlled by op-codes. These

op-codes specify the commands to the device. After

/S is activated the first byte transferred from the bus

master is the op-code. Following the op-code, any

addresses and data are then transferred.

Certain op-codes are commands with no subsequent

data transfer. The /S must go inactive after an

operation is complete and before a new op-code can

be issued. There is one valid op-code only per active

chip select.

SPI Mode 0: CPOL=0, CPHA=0

SPI Mode 3: CPOL=1, CPHA=1

Figure 2. SPI Modes 0 & 3

FM25V02 - 256Kb SPI FRAM

Rev. 0.1

Mar. 2009 Page 4 of 15

System Hookup

The SPI interface uses a total of four pins: clock,

data-in, data-out, and chip select. A typical system

configuration uses one or more FM25V02 devices

with a microcontroller that has a dedicated SPI port,

as Figure 3 illustrates. Note that the clock, data-in,

and data-out pins are common among all devices.

The Chip Select and Hold pins must be driven

separately for each FM25V02 device.

For a microcontroller that has no dedicated SPI bus, a

general purpose port may be used. To reduce

hardware resources on the controller, it is possible to

connect the two data pins together and tie off the

Hold pin. Figure 4 shows a configuration that uses

only three pins.

Figure 3. 512Kbit (64KB) System Configuration with SPI port

Figure 4. System Configuration without SPI port

FM25V02 - 256Kb SPI FRAM

Rev. 0.1

Mar. 2009 Page 5 of 15

Power Up to First Access

The FM25V02 is not accessible for a period of time

) after power up. Users must comply with the

timing parameter t

, which is the minimum time

from V

(min) to the first /S low.

Data Transfer

All data transfers to and from the FM25V02 occur in

8-bit groups. They are synchronized to the clock

signal (C), and they transfer most significant bit

(MSB) first. Serial inputs are registered on the rising

edge of C. Outputs are driven from the falling edge of

clock C.

Command Structure

There are ten commands called op-codes that can be

issued by the bus master to the FM25V02. They are

listed in the table below. These op-codes control the

functions performed by the memory. They can be

divided into three categories. First, there are

commands that have no subsequent operations. They

perform a single function, such as to enable a write

operation. Second are commands followed by one

byte, either in or out. They operate on the Status

memory transactions followed by address and one or

more bytes of data.

Table 1. Op-code Commands

Name Description Op-code

WREN

Set Write Enable Latch

0000

0110b

WRDI

Write Disable

0000

0100b

RDSR

Read Status Register

0000

0101b

WRSR

Write Status Register

0000

0001b

READ

Read Memory Data

0000

0011b

FSTRD

Fast Read Memory Data

0000

1011b

WRITE

Write Memory Data

0000

0010b

SLEEP

Enter Sleep Mode

1011

1001b

RDID

Read Device ID

1001

1111b

SNR

Read S/N

1100

0011b

WREN – Set Write Enable Latch

The FM25V02 will power up with writes disabled.

The WREN command must be issued prior to any

write operation. Sending the WREN op-code will

allow the user to issue subsequent op-codes for write

operations. These include writing the Status Register

(WRSR) and writing the memory (WRITE).

Sending the WREN op-code causes the internal Write

Enable Latch to be set. A flag bit in the Status

WEL=1 indicates that writes are permitted.

Attempting to write the WEL bit in the Status

Completing any write operation will automatically

clear the write-enable latch and prevent further

writes without another WREN command. Figure 5

below illustrates the WREN command bus

configuration.

0 0 0 0 0 1 1 0

Hi-Z

0 1 2 3 4 5 6 7

Figure 5. WREN Bus Configuration

WRDI – Write Disable

The WRDI command disables all write activity by

clearing the Write Enable Latch. The user can verify

that writes are disabled by reading the WEL bit in

the Status Register and verifying that WEL=0.

Figure 6 illustrates the WRDI command bus

configuration.

0 0 0 0 0 1 0 0

Hi-Z

0 1 2 3 4 5 6 7

Figure 6. WRDI Bus Configuration

RDSR – Read Status Register

The RDSR command allows the bus master to

verify the contents of the Status Register. Reading

Status provides information about the current state

of the write protection features. Following the

RDSR op-code, the FM25V02 will return one byte

with the contents of the Status Register. The Status

评论收藏

内容反馈

lifeng816

2018-09-04

以参考，需要修改
zhuxiaoxiaoyan

2018-02-02

一般，不知道能不能用

Lvao_qm
上传者
2018-09-18

已经在开发板上验证过的。
一路向北2007

2015-12-25

对于stm32没用

Lvao_qm
上传者
2018-09-18

修改底层驱动即可
z0704110

2015-09-09

参考后，已成功移植
mysteryarch

2015-07-19

好用，注释也比较详细，成功移植

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Lvao_qm

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