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高速ad转换芯片资料,ad9244
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2014-09-24
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fpga可以与其构成控制连接,就是你要用FPGA进行处理数据时,就需要AD转换,而AD转换的速度需要达到很高转换速度时,就可以用此芯片来解决,是14位的,65Msps采样频率
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14-Bit, 40 MSPS/65 MSPS A/D Converter
AD9244
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 © 2005 Analog Devices, Inc. All rights reserved.
FEATURES
14-bit, 40 MSPS/65 MSPS ADC
Low power
550 mW at 65 MSPS
300 mW at 40 MSPS
On-chip reference and sample-and-hold
750 MHz analog input bandwidth
SNR > 73 dBc to Nyquist @ 65 MSPS
SFDR > 86 dBc to Nyquist @ 65 MSPS
Differential nonlinearity error = ±0.7 LSB
Guaranteed no missing codes over full temperature range
1 V to 2 V p-p differential full-scale analog input range
Single 5 V analog supply, 3.3 V/5 V driver supply
Out-of-range indicator
Straight binary or twos complement output data
Clock duty cycle stabilizer
Output-enable function
48-lead LQFP package
FUNCTIONAL BLOCK DIAGRAM
CLK–
VIN+
VIN–
DCS
AGND DGNDVREF SENSE
OEB
D13 TO D0
OTR
DFS
A
VDD DRVDD
AD9244
SHA
TIMING
REFERENCE
OUTPUT
REGISTER
REF
GND
VRCML
CLK+
10-STAGE
PIPELINE ADC
REFT REFB
14
14
02404-001
Figure 1.
APPLICATIONS
Communication subsystems (microcell, picocell)
Medical and high-end imaging equipment
Test and measurement equipment
GENERAL DESCRIPTION
The AD9244 is a monolithic, single 5 V supply, 14-bit,
40 MSPS/65 MSPS ADC with an on-chip, high performance
sample-and-hold amplifier (SHA) and voltage reference.
The AD9244 uses a multistage differential pipelined architec-
ture with output error correction logic to provide 14-bit
accuracy at 40 MSPS/65 MSPS data rates, and guarantees no
missing codes over the full operating temperature range.
The AD9244 has an on-board, programmable voltage reference.
An external reference can also be used to suit the dc accuracy
and temperature drift requirements of the application.
A differential or single-ended clock input controls all internal
conversion cycles. The digital output data can be presented in
straight binary or in twos complement format. An out-of-range
(OTR) signal indicates an overflow condition that can be used
with the most significant bit to determine low or high overflow.
Fabricated on an advanced CMOS process, the AD9244 is
available in a 48-lead LQFP and is specified for operation over
the industrial temperature range (–40°C to +85°C).
PRODUCT HIGHLIGHTS
1. Low Power—The AD9244, at 550 mW, consumes a fraction
of the power of currently available ADCs in existing high
speed solutions.
2. IF Sampling—The AD9244 delivers outstanding
performance at input frequencies beyond the first Nyquist
zone. Sampling at 65 MSPS with an input frequency of
100 MHz, the AD9244 delivers 71 dB SNR and 86 dB SFDR.
3. Pin Compatibility—The AD9244 offers a seamless
migration from the 12-bit, 65 MSPS
AD9226.
4. On-Board Sample-and-Hold (SHA)—The versatile SHA
input can be configured for either single-ended or
differential inputs.
5. Out-of-Range (OTR) Indicator—The OTR output bit
indicates when the input signal is beyond the AD9244’s
input range.
6. Single Supply—The AD9244 uses a single 5 V power
supply, simplifying system power supply design. It also
features a separate digital output driver supply to
accommodate 3.3 V and 5 V logic families.
AD9244
Rev. C | Page 2 of 36
TABLE OF CONTENTS
Features .............................................................................................. 1
Functional Block Diagram .............................................................. 1
Applications....................................................................................... 1
General Description ......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
DC Specifications ......................................................................... 3
AC Specifications.......................................................................... 4
Digital Specifications ................................................................... 5
Switching Specifications .............................................................. 6
Absolute Maximum Ratings............................................................ 7
Explanation of Test Levels........................................................... 7
ESD Caution.................................................................................. 7
Pin Configuration and Function Descriptions............................. 8
Ter mi nol og y .......................................................................................9
Typical Application Circuits ......................................................... 11
Typical Performance Characteristics ........................................... 12
Theory of Operation ...................................................................... 17
Analog Input and Reference Overview ................................... 17
Analog Input Operation............................................................ 18
Reference Operation .................................................................. 20
Digital Inputs and Outputs ....................................................... 21
Evaluation Board ............................................................................ 26
Analog Input Configuration ..................................................... 26
Reference Configuration ........................................................... 26
Clock Configuration .................................................................. 26
Outline Dimensions ....................................................................... 36
Ordering Guide .......................................................................... 36
REVISION HISTORY
12/05—Rev. B to Rev. C
Updated Format..................................................................Universal
Changes to Figure 45...................................................................... 19
Added Single-Ended Input Configuration Section.................... 19
Added Reference Decoupling Section ......................................... 25
Changes to Figure 65...................................................................... 28
Changes to Figure 66...................................................................... 29
Changes to Figure 67...................................................................... 30
Added Table 15 ............................................................................... 34
2/05—Rev. A to Rev. B
Updated Format..................................................................Universal
Changes to Table 1.............................................................................3
Changes to Table 2.............................................................................4
Reformatted Table 5 ..........................................................................7
Changes to Table 6.............................................................................8
Changes to Figure 12...................................................................... 12
Changed Captions on Figure 18 and Figure 21 .......................... 13
Changes to Figure 35, Figure 38, Figure 39................................. 16
Changes to Table 9.......................................................................... 18
Changes to Table 13 ....................................................................... 26
Changes to Ordering Guide.......................................................... 36
6/03—Rev. 0 to Rev. A
Changes to AC Specifications..........................................................3
Updated Ordering Guide .................................................................6
Updated Outline Dimensions....................................................... 33
6/02—Revision 0: Initial Version
AD9244
Rev. C | Page 3 of 36
SPECIFICATIONS
DC SPECIFICATIONS
AVDD = 5 V, DRVDD = 3 V, f
SAMPLE
= 65 MSPS (–65) or 40 MSPS (–40), differential clock inputs, VREF = 2 V, external reference,
differential analog inputs, unless otherwise noted.
Table 1.
Test AD9244BST-65 AD9244BST-40
Parameter Temp Level Min Typ Max Min Typ Max Unit
RESOLUTION Full VI 14 14 Bits
DC ACCURACY
No Missing Codes Full VI Guaranteed Guaranteed Bits
Offset Error Full VI ±0.3 ±1.4 ±0.3 ±1.4 % FSR
Gain Error
1
Full VI ±0.6 ±2.0 ±0.6 ±2.0 % FSR
Differential Nonlinearity (DNL)
2
Full VI ±1.0 ±1.0 LSB
25°C V ±0.7 ±0.6 LSB
Integral Nonlinearity (INL)
2
Full V ±1.4 ±1.3 LSB
Full VI −4 +4 −4 +4 LSB
TEMPERATURE DRIFT
Offset Error Full V ±2.0 ±2.0 ppm/°C
Gain Error (EXT VREF)
1
Full V ±2.3 ±2.3 ppm/°C
Gain Error (INT VREF)
3
Full V ±25 ±25 ppm/°C
INTERNAL VOLTAGE REFERENCE
Output Voltage Error (2 VREF) Full VI ±29 ±29 mV
Load Regulation @ 1 mA Full V 0.5 0.5 mV
Output Voltage Error (1 VREF) Full IV ±15 ±15 mV
Load Regulation @ 0.5 mA Full V 0.25 0.25 mV
Input Resistance Full V 5 5 kΩ
INPUT REFERRED NOISE
VREF = 2 V 25°C V 0.8 0.8 LSB rms
VREF = 1 V 25°C V 1.5 1.5 LSB rms
ANALOG INPUT
Input Voltage Range (Differential)
VREF = 2 V Full V 2 2 V p-p
VREF = 1 V Full V 1 1 V p-p
Common-Mode Voltage Full V 0.5 4 0.5 4 V
Input Capacitance
4
25°C V 10 10 pF
Input Bias Current
5
25°C V 500 500 μA
Analog Bandwidth (Full Power) 25°C V 750 750 MHz
POWER SUPPLIES
Supply Voltages
AVDD Full IV 4.75 5 5.25 4.75 5 5.25 V
DRVDD Full IV 2.7 5.25 2.7 5.25 V
Supply Current
IAVDD Full V 109 64 mA
IDRVDD Full V 12 8 mA
PSRR Full V ±0.05 ±0.05 % FSR
POWER CONSUMPTION
DC Input
6
Full V 550 300 mW
Sine Wave Input Full VI 590 640 345 370 mW
1
Gain error is based on the ADC only (with a fixed 2.0 V external reference).
2
Measured at maximum clock rate, f
IN
= 2.4 MHz, full-scale sine wave, with approximately 5 pF loading on each output bit.
3
Includes internal voltage reference error.
4
Input capacitance refers to the effective capacitance between one differential input pin and AGND. Refer to Figure 7 for the equivalent analog input structure.
5
Input bias current is due to the input looking like a resistor that is dependent on the clock rate.
6
Measured with dc input at maximum clock rate.
AD9244
Rev. C | Page 4 of 36
AC SPECIFICATIONS
AVDD = 5 V, DRVDD = 3 V, f
SAMPLE
= 65 MSPS (–65) or 40 MSPS (–40), differential clock inputs, VREF = 2 V, external reference,
A
IN
= –0.5 dBFS, differential analog inputs, unless otherwise noted.
Table 2.
Test AD9244BST-65 AD9244BST-40
Parameter Temp Level Min Typ Max Min Typ Max Unit
SNR
1
f
IN
= 2.4 MHz Full VI 72.4 73.4 dBc
25°C I 74.8 75.3 dBc
f
IN
= 15.5 MHz (–1 dBFS) Full IV 72.0 dBc
25°C V 73.7 dBc
f
IN
= 20 MHz Full VI 72.1 dBc
25°C I 74.7 dBc
f
IN
= 32.5 MHz Full IV 70.8 dBc
25°C I 73.0 dBc
f
IN
= 70 MHz Full IV 69.9 dBc
25°C V 72.2 dBc
f
IN
= 100 MHz 25°C V 71.2 72.8 dBc
f
IN
= 200 MHz 25°C V 67.2 68.3 dBc
SINAD
1
f
IN
= 2.4 MHz Full VI 72.2 73.2 dBc
25°C I 74.7 75.1 dBc
f
IN
= 20 MHz Full VI 72 dBc
25°C I 74.4 dBc
f
IN
= 32.5 MHz Full IV 70.6 dBc
25°C I 72.6 dBc
f
IN
= 70 MHz Full IV 69.7 dBc
25°C V 71.9 dBc
f
IN
= 100 MHz 25°C V 71 72.4 dBc
f
IN
= 200 MHz 25°C V 59.8 56.3 dBc
ENOB
f
IN
= 2.4 MHz Full VI 11.7 11.9 Bits
25°C I 12.1 12.2 Bits
f
IN
= 20 MHz Full VI 11.7 Bits
25°C I 12.1 Bits
f
IN
= 32.5 MHz Full IV 11.4 Bits
25°C I 11.8 Bits
f
IN
= 70 MHz Full IV 11.3 Bits
25°C V 11.7 Bits
f
IN
= 100 MHz 25°C V 11.5 11.7 Bits
f
IN
= 200 MHz 25°C V 9.6 9.1 Bits
THD
1
f
IN
= 2.4 MHz Full VI −78.4 −80.7 dBc
25°C I −90.0 −89.7 dBc
f
IN
= 20 MHz Full VI −80.4 dBc
25°C I −89.4 dBc
f
IN
= 32.5 MHz Full IV −79.2 dBc
25°C I −84.6 dBc
f
IN
= 70 MHz Full IV −78.7 dBc
25°C V −84.1 dBc
f
IN
= 100 MHz 25°C V −83.0 −83.2 dBc
f
IN
= 200 MHz 25°C V −60.7 −56.6 dBc
AD9244
Rev. C | Page 5 of 36
Test AD9244BST-65 AD9244BST-40
Parameter Temp Level Min Typ Max Min Typ Max Unit
WORST HARMONIC (SECOND or THIRD)
1
f
IN
= 2.4 MHz 25°C V −94.5 −93.7 dBc
f
IN
= 20 MHz 25°C V −92.8 dBc
f
IN
= 32.5 MHz 25°C V −86.5 dBc
f
IN
= 70 MHz 25°C V −86.1 dBc
f
IN
= 100 MHz 25°C V −86.2 −84.5 dBc
f
IN
= 200 MHz 25°C V −60.7 −56.6 dBc
SFDR
1
f
IN
= 2.4 MHz Full VI 78.6 82.5 dBc
25°C I 94.5 93.7 dBc
f
IN
= 15.5 MHz (–1 dBFS) Full IV 83 dBc
25°C V 90 dBc
f
IN
= 20 MHz Full IV 81.4 dBc
25°C I 91.8 dBc
f
IN
= 32.5 MHz Full IV 80.0 dBc
25°C I 86.4 dBc
f
IN
= 70 MHz Full IV 79.5 dBc
25°C V 86.1 dBc
f
IN
= 100 MHz 25°C V 86.2 84.5 dBc
f
IN
= 200 MHz 25°C V 60.7 56.6 dBc
1
AC specifications can be reported in dBc (degrades as signal levels are lowered) or in dBFS (always related back to converter full scale).
DIGITAL SPECIFICATIONS
AVDD = 5 V, DRVDD = 3 V, VREF = 2 V, external reference, unless otherwise noted.
Table 3.
Test AD9244BST-65 AD9244BST-40
Parameter Temp Level Min Typ Max Min Typ Max Unit
DIGITAL INPUTS
Logic 1 Voltage (OEB, DRVDD = 3 V) Full IV 2 2 V
Logic 1 Voltage (OEB, DRVDD = 5 V) Full IV 3.5 3.5 V
Logic 0 Voltage (OEB) Full IV 0.8 0.8 V
Logic 1 Voltage (DFS, DCS) Full IV 3.5 3.5 V
Logic 0 Voltage (DFS, DCS) Full IV 0.8 0.8 V
Input Current Full IV 10 10 μA
Input Capacitance Full V 5 5 pF
CLOCK INPUT PARAMETERS
Differential Input Voltage Full IV 0.4 0.4 V p-p
CLK− Voltage
1
Full IV 0.25 0.25 V
Internal Clock Common-Mode Full V 1.6 1.6 V
Single-Ended Input Voltage
Logic 1 Voltage Full IV 2 2 V
Logic 0 Voltage Full IV 0.8 0.8 V
Input Capacitance Full V 5 5 pF
Input Resistance Full V 100 100 kΩ
DIGITAL OUTPUTS (DRVDD = 5 V)
Logic 1 Voltage (I
OH
= 50 μA) Full IV 4.5 4.5 V
Logic 0 Voltage (I
OL
= 50 μA) Full IV 0.1 0.1 V
Logic 1 Voltage (I
OH
= 0.5 mA) Full IV 2.4 2.4 V
Logic 0 Voltage (I
OL
= 1.6 mA) Full IV 0.4 0.4 V
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