松翰8位FLASH单片机SN8F27E65L资源-CSDN文库

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1.1 FEATURES  Memory configuration  Four 8-bit timer. (T0, TC0, TC1, TC2). Flash ROM size: 6K x 16 bits. Including EEROM T0: Basic timer. emulation. (In system programming) TC0: Timer/counter/PWM0. RAM size: 512 x 8 bits. TC1: Timer/counter/PWM1.  8 levels stack buffer. TC2: Timer/counter/PWM2  13 interrupt sources  3 channel duty/cycle programmable PWM to 11 internal interrupts: T0, TC0, TC1, TC2, T1, ADC, Generate PWM, Buzzer and IR carrier signals. SIO, MSP, UTX(UART TX), URX(UART RX), WAKE (PWM0~2). 2 external interrupts: INT0, INT1  One 16-bit timer (T1) with capture timer function  Multi-interrupt vector structure.  12- channel 10-bit SAR ADC. Each of interrupt sources has a unique interrupt vector.  Serial Interface: SIO, UART, MSP  Build in Embedded ICE function.  I/O pin configuration Bi-directional: P0, P1, P4, P5.  Four system clocks Wakeup: P0, P1 level change. External high clock: RC type up to 10MHz Pull-up resisters: P0, P1, P4, P5. External high clock: Crystal type up to 16MHz External interrupt: P0.0, P0.1 Internal high clock: RC type 16MHz ADC input pin: AIN0~AIN11. Internal low clock: RC type 16KHz  Four operating modes  Fcpu (Instruction cycle) Normal mode: Both high and low clock active Fcpu = Fhosc/1, Fhosc/2, Fhosc/4, Fhosc/8, Fhosc/16, Slow mode: Low clock only Fhosc/32, Fhosc/64, Fhosc/128 Sleep mode: Both high and low clock stop  On chip watchdog timer and clock source Green mode: Periodical wakeup by timer  1.8V/2.4V/3.3V 3-level LVD with trim.  Package (Chip form support) PDIP 32 pin  Powerful instructions LQFP 32 pin Instruction’s length is one word. QFN 32 pin Most of instructions are one cycle only. SKDIP 28 pin All ROM area JMP instruction. SOP 28 pin All ROM area lookup table function (MOVC). SSOP 28 pin QFN 28 pin DIP 20 pin SOP 20 pin

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SN8F27E60 Series

8-Bit Flash Micro-Controller with Embedded ICE and ISP

SONiX TECHNOLOGY CO., LTD Page 1 Preliminary Version 0.4

SN8F27E60 Series

USER’S MANUAL

Preliminary Version 0.4

SN8F27E65

SN8F27E64

SN8F27E62

SN8F27E65L

SN8F27E64L

SN8F27E62L

SONIX reserves the right to make change without further notice to any products herein to improve reliability, function or design. SONIX does not

assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent

rights nor the rights of others. SONIX products are not designed, intended, or authorized for us as components in systems intended, for surgical

implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SONIX product

could create a situation where personal injury or death may occur. Should Buyer purchase or use SONIX products for any such unintended or

unauthorized application. Buyer shall indemnify and hold SONIX and its officers, employees, subsidiaries, affiliates and distributors harmless against

all claims, cost, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death

associated with such unintended or unauthorized use even if such claim alleges that SONIX was negligent regarding the design or manufacture of

the part.

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SN8F27E60 Series

8-Bit Flash Micro-Controller with Embedded ICE and ISP

SONiX TECHNOLOGY CO., LTD Page 3 Preliminary Version 0.4

Table of Content

AMENDENT HISTORY ................................................................................................................................ 2

PRODUCT OVERVIEW .............................................................................................................................. 10

1.1 FEATURES ............................................................................................................................................ 10

1.2 SYSTEM BLOCK DIAGRAM .............................................................................................................. 12

1.3 PIN ASSIGNMENT ............................................................................................................................... 13

1.4 PIN DESCRIPTIONS ............................................................................................................................. 15

1.5 PIN CIRCUIT DIAGRAMS ................................................................................................................... 16

CENTRAL PROCESSOR UNIT (CPU) ....................................................................................................... 18

2.1 PROGRAM MEMORY (FLASH ROM) ................................................................................................ 18

2.1.1 RESET VECTOR (0000H) ............................................................................................................. 19

2.1.2 INTERRUPT VECTOR (0008H~0014H) ....................................................................................... 20

2.1.3 LOOK-UP TABLE DESCRIPTION ............................................................................................... 22

2.1.4 JUMP TABLE DESCRIPTION ...................................................................................................... 24

2.1.5 CHECKSUM CALCULATION...................................................................................................... 26

2.2 DATA MEMORY (RAM) ...................................................................................................................... 27

2.2.1 SYSTEM REGISTER ..................................................................................................................... 28

2.2.1.1 SYSTEM REGISTER TABLE ................................................................................................ 28

2.2.1.2 SYSTEM REGISTER DESCRIPTION ................................................................................... 28

2.2.1.3 BIT DEFINITION of SYSTEM REGISTER ........................................................................... 29

2.2.2 ACCUMULATOR .......................................................................................................................... 31

2.2.3 PROGRAM FLAG .......................................................................................................................... 32

2.2.4 PROGRAM COUNTER.................................................................................................................. 33

2.2.5 H, L REGISTERS............................................................................................................................ 36

2.2.6 X REGISTERS ................................................................................................................................ 37

2.2.7 Y, Z REGISTERS............................................................................................................................ 37

2.2.8 R REGISTER .................................................................................................................................. 38

2.2.9 W REGISTERS ............................................................................................................................... 39

2.3 ADDRESSING MODE .......................................................................................................................... 40

2.3.1 IMMEDIATE ADDRESSING MODE ........................................................................................... 40

2.3.2 DIRECTLY ADDRESSING MODE .............................................................................................. 40

2.3.3 INDIRECTLY ADDRESSING MODE .......................................................................................... 40

2.4 STACK OPERATION ............................................................................................................................ 41

2.4.1 OVERVIEW .................................................................................................................................... 41

2.4.2 STACK POINTER .......................................................................................................................... 41

2.4.3 STACK BUFFER ............................................................................................................................ 42

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8-Bit Flash Micro-Controller with Embedded ICE and ISP

SONiX TECHNOLOGY CO., LTD Page 4 Preliminary Version 0.4

2.4.4 STACK OVERFLOW INDICATOR .............................................................................................. 42

2.4.5 STACK OPERATION EXAMPLE................................................................................................. 43

2.5 CODE OPTION TABLE ........................................................................................................................ 44

2.5.1 Fcpu Code Option ............................................................................................................................ 45

2.5.2 Reset_Pin code option ..................................................................................................................... 45

2.5.3 Security code option ........................................................................................................................ 45

2.5.4 Noise Filter code option .................................................................................................................. 45

RESET ........................................................................................................................................................... 46

3.1 OVERVIEW ........................................................................................................................................... 46

3.2 POWER ON RESET ............................................................................................................................... 47

3.3 WATCHDOG RESET ............................................................................................................................ 47

3.4 BROWN OUT RESET ........................................................................................................................... 47

3.4.1 THE SYSTEM OPERATING VOLTAGE ..................................................................................... 48

3.4.2 LOW VOLTAGE DETECTOR (LVD) .......................................................................................... 48

3.4.3 BROWN OUT RESET IMPROVEMENT ..................................................................................... 50

3.5 EXTERNAL RESET .............................................................................................................................. 51

3.6 EXTERNAL RESET CIRCUIT ............................................................................................................. 51

3.6.1 Simply RC Reset Circuit ................................................................................................................. 51

3.6.2 Diode & RC Reset Circuit ............................................................................................................... 52

3.6.3 Zener Diode Reset Circuit ............................................................................................................... 52

3.6.4 Voltage Bias Reset Circuit .............................................................................................................. 53

3.6.5 External Reset IC ............................................................................................................................. 53

SYSTEM CLOCK ......................................................................................................................................... 54

4.1 OVERVIEW ........................................................................................................................................... 54

4.2 FCPU (INSTRUCTION CYCLE) ............................................................................................................ 54

4.3 NOISE FILTER ...................................................................................................................................... 54

4.4 SYSTEM HIGH-SPEED CLOCK .......................................................................................................... 54

4.4.1 HIGH_CLK CODE OPTION .......................................................................................................... 55

4.4.2 INTERNAL HIGH-SPEED OSCILLATOR RC TYPE (IHRC) .................................................... 55

4.4.3 EXTERNAL HIGH-SPEED OSCILLATOR .................................................................................. 55

4.4.4 EXTERNAL OSCILLATOR APPLICATION CIRCUIT .............................................................. 55

4.5 SYSTEM LOW-SPEED CLOCK ........................................................................................................... 56

4.6 OSCM REGISTER ................................................................................................................................. 56

4.7 SYSTEM CLOCK MEASUREMENT ................................................................................................... 57

4.8 SYSTEM CLOCK TIMING ................................................................................................................... 57

SYSTEM OPERATION MODE ................................................................................................................... 60

5.1 OVERVIEW ........................................................................................................................................... 60

5.2 NORMAL MODE .................................................................................................................................. 61

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8-Bit Flash Micro-Controller with Embedded ICE and ISP

SONiX TECHNOLOGY CO., LTD Page 5 Preliminary Version 0.4

5.3 SLOW MODE ........................................................................................................................................ 62

5.4 POWER DOWN MDOE ......................................................................................................................... 62

5.5 GREEN MODE ...................................................................................................................................... 63

5.6 OPERATING MODE CONTROL MACRO .......................................................................................... 64

5.7 WAKEUP ............................................................................................................................................... 65

5.7.1 OVERVIEW .................................................................................................................................... 65

5.7.2 WAKEUP TIME ............................................................................................................................. 65

5.7.3 P1W WAKEUP CONTROL REGISTER ....................................................................................... 66

INTERRUPT ................................................................................................................................................. 67

6.1 OVERVIEW ........................................................................................................................................... 67

6.2 INTERRUPT OPERATION ........................................................................................................................... 67

6.3 INTEN INTERRUPT ENABLE REGISTER ......................................................................................... 68

6.4 INTRQ INTERRUPT REQUEST REGISTER ....................................................................................... 69

6.5 GIE GLOBAL INTERRUPT OPERATION .......................................................................................... 70

6.6 EXTERNAL INTERRUPT OPERATION (INT0~INT1) ...................................................................... 71

6.7 T0 INTERRUPT OPERATION .............................................................................................................. 72

6.8 TC0 INTERRUPT OPERATION ........................................................................................................... 73

6.9 TC1 INTERRUPT OPERATION ........................................................................................................... 74

6.10 TC2 INTERRUPT OPERATION ......................................................................................................... 75

6.11 T1 INTERRUPT OPERATION ............................................................................................................ 76

6.12 ADC INTERRUPT OPERATION ........................................................................................................ 77

6.13 SIO INTERRUPT OPERATION .......................................................................................................... 78

6.14 UART INTERRUPT OPERATION ..................................................................................................... 79

6.15 MULTI-INTERRUPT OPERATION ................................................................................................... 80

I/O PORT ....................................................................................................................................................... 81

7.1 OVERVIEW ........................................................................................................................................... 81

7.2 I/O PORT MODE ................................................................................................................................... 82

7.3 I/O PULL UP REGISTER ...................................................................................................................... 83

7.4 I/O PORT DATA REGISTER ................................................................................................................ 84

7.5 PORT 4, PORT 5 ADC SHARE PIN ........................................................................................................ 85

7.6 OPEN-DRAIN REGISTER .................................................................................................................... 87

TIMERS......................................................................................................................................................... 88

8.1 WATCHDOG TIMER ............................................................................................................................ 88

8.2 T0 8-BIT BASIC TIMER .............................................................................................................................. 90

8.2.1 OVERVIEW .................................................................................................................................... 90

8.2.2 T0 Timer Operation ......................................................................................................................... 91

8.2.3 T0M MODE REGISTER ................................................................................................................ 92

8.2.4 T0C COUNTING REGISTER ........................................................................................................ 92

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