VHDL测试代码对FPGA数码管显示功能进行测试

1。编写VHDL测试代码对FPGA0数码管显示功能进行测试

程序：
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity fpga0x is
    Port ( k0 : in std_logic_vector(7 downto 0);
           k1 : in std_logic_vector(7 downto 0);
           k2 : in std_logic_vector(7 downto 0);
           k3 : in std_logic_vector(7 downto 0);
           k4 : in std_logic_vector(7 downto 0);
           s0 : out std_logic_vector(7 downto 0);
           s1 : out std_logic_vector(7 downto 0);
           s2 : out std_logic_vector(7 downto 0);
           s3 : out std_logic_vector(7 downto 0);
           s4 : out std_logic_vector(7 downto 0);
           s5 : out std_logic_vector(7 downto 0);
           B : out std_logic_vector(7 downto 0);
           A : out std_logic_vector(7 downto 0));
end fpga0x;

architecture Behavioral of fpga0x is

begin
OK: FOR i in 0 to 7 generate 
      s0(i)<=k0(i);
      s3(i)<=k0(i);
      s1(i)<=k1(i);
   s4(i)<=k1(i);
   s2(i)<=k2(i);
   s5(i)<=k2(i);
   B(i)<=k3(i);
   A(i)<=k4(i);
end generate OK ;

end Behavioral;


管脚（UCF文件）：
NET "K0<7>" LOC =P94;
NET "K0<6>" LOC =P95;
NET "K0<5>" LOC =P96;
NET "K0<4>" LOC =P97;
NET "K0<3>" LOC =P100;
NET "K0<2>" LOC =P101;
NET "K0<1>" LOC =P102;
NET "K0<0>" LOC =P103;
NET "K1<7>" LOC =P79;
NET "K1<6>" LOC =P80;
NET "K1<5>" LOC =P81;
NET "K1<4>" LOC =P82;
NET "K1<3>" LOC =P84;