Intel® 64 and IA-32 Architectures
Software Developer’s Manual
Volume 2B:
Instruction Set Reference, N-Z
NOTE: The Intel 64 and IA-32 Architectures Software Developer's Manual
consists of five volumes: Basic Architecture, Order Number 253665;
Instruction Set Reference A-M, Order Number 253666; Instruction Set
Reference N-Z, Order Number 253667; System Programming Guide,
Part 1, Order Number 253668; System Programming Guide, Part 2,
Order Number 253669. Refer to all five volumes when evaluating your
design needs.
Order Number: 253667-028US
September 2008
ii Vol. 2B
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Vol. 2B 4-1
CHAPTER 4
INSTRUCTION SET REFERENCE, N-Z
4.1 INSTRUCTIONS (N-Z)
Chapter 4 continues an alphabetical discussion of Intel
®
64 and IA-32 instructions
(N-Z). See also:
Chapter 3, “Instruction Set Reference, A-M,” in the Intel® 64 and
IA-32 Architectures Software Developer’s Manual, Volume 2A.
4-2 Vol. 2B
NEG—Two's Complement Negation
INSTRUCTION SET REFERENCE, N-Z
NEG—Two's Complement Negation
Description
Replaces the value of operand (the destination operand) with its two's complement.
(This operation is equivalent to subtracting the operand from 0.) The destination
operand is located in a general-purpose register or a memory location.
This instruction can be used with a LOCK prefix to allow the instruction to be
executed atomically.
In 64-bit mode, the instruction’s default operation size is 32 bits. Using a REX prefix
in the form of REX.R permits access to additional registers (R8-R15). Using a REX
prefix in the form of REX.W promotes operation to 64 bits. See the summary chart at
the beginning of this section for encoding data and limits.
Operation
IF DEST = 0
THEN CF ← 0;
ELSE CF ← 1;
FI;
DEST ← [– (DEST)]
Flags Affected
The CF flag set to 0 if the source operand is 0; otherwise it is set to 1. The OF, SF, ZF,
AF, and PF flags are set according to the result.
Opcode Instruction 64-Bit Mode Compat/
Leg Mode
Description
F6 /3 NEG r/m8 Valid Valid Two's complement negate r/m8.
REX + F6 /3 NEG r/m8* Valid N.E. Two's complement negate r/m8.
F7 /3 NEG r/m16 Valid Valid Two's complement negate
r/m16.
F7 /3 NEG r/m32 Valid Valid Two's complement negate
r/m32.
REX.W + F7 /3 NEG r/m64 Valid N.E. Two's complement negate
r/m64.
NOTES:
* In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix is
used: AH, BH, CH, DH.
Vol. 2B 4-3
INSTRUCTION SET REFERENCE, N-Z
NEG—Two's Complement Negation
Protected Mode Exceptions
#GP(0) If the destination is located in a non-writable segment.
If a memory operand effective address is outside the CS, DS,
ES, FS, or GS segment limit.
If the DS, ES, FS, or GS register contains a NULL segment
selector.
#SS(0) If a memory operand effective address is outside the SS
segment limit.
#PF(fault-code) If a page fault occurs.
#AC(0) If alignment checking is enabled and an unaligned memory
reference is made while the current privilege level is 3.
#UD If the LOCK prefix is used but the destination is not a memory
operand.
Real-Address Mode Exceptions
#GP If a memory operand effective address is outside the CS, DS,
ES, FS, or GS segment limit.
#SS If a memory operand effective address is outside the SS
segment limit.
#UD If the LOCK prefix is used but the destination is not a memory
operand.
Virtual-8086 Mode Exceptions
#GP(0) If a memory operand effective address is outside the CS, DS,
ES, FS, or GS segment limit.
#SS(0) If a memory operand effective address is outside the SS
segment limit.
#PF(fault-code) If a page fault occurs.
#AC(0) If alignment checking is enabled and an unaligned memory
reference is made.
#UD If the LOCK prefix is used but the destination is not a memory
operand.
Compatibility Mode Exceptions
Same as for protected mode exceptions.
64-Bit Mode Exceptions
#SS(0) If a memory address referencing the SS segment is in a non-
canonical form.
#GP(0) If the memory address is in a non-canonical form.
#PF(fault-code) For a page fault.
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