TC358870XBG
1 2015-02-02
© 2014 Toshiba Corporation
CMOS Digital Integrated Circuit Silicon Monolithic
TC358870XBG Mobile Peripheral Devices
Overview
TC358870XBG, Ultra HD to DSI, bridge converts high resolution (higher
than 4 Gbps) HDMI® stream to MIPI DSI Tx video. It is a follow up device
of TC358779XBG, without scalar functionality. The HDMI-RX runs at 297
MHz to carry up to 7.2 Gbps video stream. It requires dual link MIPI DSI Tx,
1 Gbps/data lane, to transmit out a maximum 7.2 Gbps video data.
The bridge chip is necessary for current and next generation Application Processors to drive a (dual) DSI link
display by using its HDMI Tx output port.
Features
● HDMI-RX Interface
HDMI 1.4b
- Video Formats Support (Up to 4K×2K / 30fps),
maximum 24 bps (bit-per-pixel) no deep color
support
RGB, YCbCr444: 24-bpp
YCbCr422: 24-bpp
- Color Conversion
4:2:2 to 4:4:4 is supported
4:4:4: to 4:2:2 is supported
RGB888 to YCbCr (4:4:4 / 4:2:2) is supported
YCbCr (4:4:4 / 4:2:2) to RGB888/666 is
supported
Note: for RGB666 (R=R[5:0],2'b00,
G=G[5:0],2'b00, B=G[5:0],2'b00)
- Maximum HDMI clock speed: 297 MHz
- Audio Supports
Internal Audio PLL to track N/CTS value
transmitted by the ACR packet.
- 3D Support
- Support HDCP1.4 decryptions
- EDID Support, Release A, Revision 1 (Feb 9,
2000)
First 128 byte (EDID 1.3 structure)
First E-EDID Extension: 128 bytes of CEA
Extension version 3 (specified in CEA-861-D)
Embedded 1K-byte SRAM (EDID_SRAM)
Does not support Audio Return Path and HDMI
Ethernet Channels
● DSI TX Interface
MIPI DSI compliant (Version 1.1 22 November
2011)
Dual links DSI (DSI0 and DSI1), each link supports
4 data lanes @1 Gbps/ data lane
- DSI0 carries the left half data of HDMI Rx video
stream and DSI1 carries the right one at the
default configuration.
- Left or right data can be assigned/programmed to
either DSI Tx link
- The maximum length of each half is limited to
2048-pixel plus up to full length overlap, DSI0
data length could be different from that of DSI1's
- The maximum Hsync skew between DSI0 and
DSI1 can be less than 10 ByteClk
Single link DSI, maximum horizontal pixel width
- 2558 pixels (24-bit per pixel)
- 3411 pixels (16-bit per pixel)
Supports video data formats
- RGB666, RGB888, YCbCr444, YCbCr 422
16-bit and YCbCr 422 24-bit
- YCbCr inputs can be converted into RGB before
outputting
● I
2
C Interface
Support for normal (100 kHz), fast mode (400 kHz)
and ultrafast mode (2 MHz)
Slave Mode
- To be used by an external Master to configure all
TC358870XBG internal registers, including
EDID_SRAM and panel control
- Support 2 I
2
C Slave Addresses (0x0F & 0x1F)
selected through boot-strap pin (INT)
● Audio Output Interface
Up to four I2S data lines for supporting
multi-Channel audio data (5.1 and 7.1)
Maximum audio sample frequency supported is 192
kHz @8 CH
Support 16, 18, 20 or 24-bit data (depend on HDMI
input stream)
Support Master Clock output only
Support 32 bit-wide time-slot only
Output Audio Over Sampling clock (256fs)
Either I2S or TDM Audio interface available (pins
are multiplexed)
I2S Audio Interface
- Support Left or Right-justify with MSB first
TDM (Time Division Multiplexed) Audio Interface
- Fixed to 8 channels (depend on HDMI input
stream)
P-VFBGA80-0707-0.65-001
Weight: 67.1 mg (Typ.)
TC358870XBG
TC358870XBG
2 2015-02-02
© 2014 Toshiba Corporation
Digital Audio Interface
- Supports HBR audio stream split across 4 I2S
lines if bandwidth higher than 12 MHz
● InfraRed (IR)
Support NEC InfraRed protocol.
● Power supply inputs
Core: 1.15V
MIPI D-PHY: 1.2V
I/O: 1.8V, 3.3V
HDMI: 3.3V
APLL: 3.3V
● Power Consumption during typical operations
1920×1080 @60 fps: 420 mW (Dual D-PHY link)
2560×1600 @60 fps: 504 mW (Dual D-PHY link)
3840×2160 @30 fps: 520 mW (Dual D-PHY link)
TC358870XBG
3 2015-02-02
Table of content
REFERENCES ................................................................................................................................................... 20
1. Overview ........................................................................................................................................................ 21
2. External Pins .................................................................................................................................................. 22
2.1. TC358870XBG 80-Pin Count Summary ................................................................................................. 24
2.2. Pin Layout ................................................................................................................................................ 24
3. Major Functional Blocks ................................................................................................................................. 25
3.1. HDMI-RX ................................................................................................................................................. 26
3D Support ................................................................................................................................................................. 26 3.1.1.
InfoFrame Data........................................................................................................................................................... 26 3.1.2.
3.2. Line Split .................................................................................................................................................. 28
3.3. DSI Tx Controller ..................................................................................................................................... 30
DSI TX Application ..................................................................................................................................................... 30 3.3.1.
3.3.1.1. Program/Initialize DSI Panel.......................................................................................................................................... 30
DSI TX Command Packet Operation .......................................................................................................................... 30 3.3.2.
TX Short Packet (DCS) Write Command .................................................................................................................... 31 3.3.3.
TX Long Packet Write Command (limited to 512-byte in length) ................................................................................ 32 3.3.4.
LPRX Packet Read Command ................................................................................................................................... 34 3.3.5.
3D Support ................................................................................................................................................................. 35 3.3.6.
3.4. CEC Controller ........................................................................................................................................ 35
Receive Operation Sequence ..................................................................................................................................... 35 3.4.1.
3.4.1.1. Noise cancellation time ................................................................................................................................................. 36
3.4.1.2. Start bit detection .......................................................................................................................................................... 36
3.4.1.3. Waveform Error Detection ............................................................................................................................................. 37
3.4.1.4. Data sampling timing ..................................................................................................................................................... 37
Transmit Operation Sequence .................................................................................................................................... 38 3.4.2.
3.4.2.1. Wait Time for Bus to be Free......................................................................................................................................... 38
3.4.2.2. Transmission Timing ..................................................................................................................................................... 39
Arbitration lost............................................................................................................................................................. 39 3.4.3.
Low level functions ..................................................................................................................................................... 40 3.4.4.
3.5. Audio Output Function ............................................................................................................................. 41
I2S Interface ............................................................................................................................................................... 41 3.5.1.
3.5.1.1. Normal Mode ................................................................................................................................................................. 41
3.5.1.2. HBR Split over I2S ........................................................................................................................................................ 44
TDM (Time Division Multiplexed) Audio Interface ....................................................................................................... 45 3.5.2.
3.6. InfraRed (IR) Interface ............................................................................................................................. 46
Programmable timing ................................................................................................................................................. 47 3.6.1.
Basic Operation .......................................................................................................................................................... 48 3.6.2.
3.7. I
2
C ............................................................................................................................................................ 48
Providing Register Address over I
2
C Bus ................................................................................................................... 49 3.7.1.
I
2
C Write Access Translation ...................................................................................................................................... 50 3.7.2.
I
2
C Read Access Translation ...................................................................................................................................... 50 3.7.3.
4. Clock and System .......................................................................................................................................... 51
TC358870XBG
4 2015-02-02
4.1. Clocks Generation ................................................................................................................................... 53
CEC clock divider configuration .................................................................................................................................. 53 4.1.1.
IR clock divider configuration ...................................................................................................................................... 53 4.1.2.
DSI PLL configuration ................................................................................................................................................. 53 4.1.3.
Audio PLL configuration ............................................................................................................................................. 53 4.1.4.
4.2. Power Up Procedure ............................................................................................................................... 54
4.3. Power Down Procedure .......................................................................................................................... 55
5. RegFile Block (Reg) ....................................................................................................................................... 56
5.1. Register Map ........................................................................................................................................... 56
5.2. Global ...................................................................................................................................................... 57
Chip and Revision ID (ChipID: 0x0000) ...................................................................................................................... 57 5.2.1.
System Control Register (SysCtl: 0x0002) ................................................................................................................. 58
5.2.2.
Configuration Control Register 0 (ConfCtl0: 0x0004) ................................................................................................. 59 5.2.3.
Configuration Control Register 1(ConfCtl1: 0x0006) .................................................................................................. 60 5.2.4.
I2S_IO_CTL (I2S_IO_CTL: 0x0072) ........................................................................................................................... 61 5.2.5.
I2S PUDCTL (I2S PUDCTL: 0x0084) ......................................................................................................................... 61 5.2.6.
I2S Control Register (I2SCtl: 0x7082) ........................................................................................................................ 62 5.2.7.
5.3. Interrupt Registers ................................................................................................................................... 63
Interrupt Status Register (IntStatus: 0x0014) ............................................................................................................. 63 5.3.1.
Interrupt Mask Register (IntMask: 0x0016) ................................................................................................................. 64 5.3.2.
Interrupt Flag Register (IntFlag: 0x0018) .................................................................................................................... 64 5.3.3.
SYS Interrupt Status Register (IntSYSStatus: 0x001A) .............................................................................................. 65 5.3.4.
5.4. IR Registers ............................................................................................................................................. 66
IR Clock High Time Register 0 (IrHclk: 0x002C)......................................................................................................... 66 5.4.1.
IR Clock Low Time Register 0 (IrLclk: 0x002E)........................................................................................................ 66 5.4.2.
IR Lead Code HMin Register (LCHmin: 0x0034) ..................................................................................................... 66 5.4.3.
IR Lead Code HMax Register (LCHmax: 0x0036) ................................................................................................... 67 5.4.4.
IR Lead Code LMin Register (LCLmin: 0x0038) ...................................................................................................... 67 5.4.5.
IR Lead Code LMax Register (LCLmax: 0x003A) .................................................................................................... 67 5.4.6.
IR Bit “H” HMin Register (BHHmin: 0x003C) .............................................................................................................. 68 5.4.7.
IR Bit “H” H Max Register (BHHmax: 0x003E) ........................................................................................................... 68 5.4.8.
IR Bit “H” LMin Register (BHLmin: 0x0040) ............................................................................................................. 68 5.4.9.
IR Bit “H” LMax Register (BHLmax: 0x0042) ............................................................................................................ 69 5.4.10.
IR Bit “L” HMin Register (BLHmin: 0x0044) ........................................................................................................... 69 5.4.11.
IR Bit “L” HMax Register (BLHmax: 0x0046) ......................................................................................................... 69 5.4.12.
IR Bit “L” LMin Register (BLLmin: 0x0048) ............................................................................................................ 70 5.4.13.
IR Bit “L” LMax Register (BLLmax: 0x004A) ............................................................................................................. 70 5.4.14.
IR “END” HMin Register (EndHmin: 0x004C) ........................................................................................................ 70 5.4.15.
IR “END” HMax Register (EndHmax: 0x004E) ....................................................................................................... 71 5.4.16.
IR Repeat Code LMin Register (RCLmin: 0x0050) ................................................................................................ 71 5.4.17.
IR Repeat Code LMax Register (RCLmax: 0x0052) .............................................................................................. 71 5.4.18.
IR Control Register (IRCtl: 0x0058) .......................................................................................................................... 72 5.4.19.
IR Data Register (IRData: 0x005A) .......................................................................................................................... 72 5.4.20.
IR CONTROL REGISTER (IR_CONTROL: 0x7082) ................................................................................................ 72 5.4.21.
TC358870XBG
5 2015-02-02
5.5. DSI-TX0 Registers ................................................................................................................................... 73
DSI-TX0 Control Registers ......................................................................................................................................... 73 5.5.1.
5.5.1.1. DSITX_CLKEN (0x0108) ............................................................................................................................................... 73
5.5.1.2. PPI_CLKSEL (0x010C) ................................................................................................................................................. 74
5.5.1.3. MODE_CONFIG (0x0110) ............................................................................................................................................ 75
5.5.1.4. LANE_ENABLE (0x0118) .............................................................................................................................................. 76
5.5.1.5. DSITX_START (0x011C) .............................................................................................................................................. 77
5.5.1.6. LINE_INIT_COUNT (0x0120) ........................................................................................................................................ 77
5.5.1.7. HSTX_TO_COUNT (0x0124) ........................................................................................................................................ 79
5.5.1.8. FUNC_ENABLE (0x0128) ............................................................................................................................................. 80
5.5.1.9. DSI_LPTX_MODE (0x012C) ......................................................................................................................................... 81
5.5.1.10. DSI_PRESP_LPW_COUNT (0x013C) ........................................................................................................................ 82
5.5.1.11. DSI_PRESP_HSR_COUNT (0x0140) ......................................................................................................................... 82
5.5.1.12. DSI_PRESP_HSW_COUNT (0x0144) ........................................................................................................................ 83
5.5.1.13. FUNC_MODE (0x0150) .............................................................................................................................................. 83
5.5.1.14. DSIRX_VC_ENABLE (0x0154) ................................................................................................................................... 84
5.5.1.15. IND_TO_COUNT (0x0158) ......................................................................................................................................... 86
5.5.1.16. INIT_INT_STAT (0x0160)............................................................................................................................................ 87
5.5.1.17. INIT_INT_MASK (0x0164)........................................................................................................................................... 88
APF Configuration Registers ...................................................................................................................................... 89 5.5.2.
5.5.2.1. APF_VDELAYCNT (0x0170) ......................................................................................................................................... 89
5.5.2.2. APF_VC_CONFIG (0x0178) ......................................................................................................................................... 89
5.5.2.3. DSITX_MODE (0x017C) ............................................................................................................................................... 90
5.5.2.4. DSI_HSYNC_WIDTH (0x018C) .................................................................................................................................... 91
5.5.2.5. DSI_HBPR (0x0190) ..................................................................................................................................................... 91
RX Event Registers .................................................................................................................................................... 92 5.5.3.
5.5.3.1. DSI_RX_STATE_INT_STAT (0x01A0) .......................................................................................................................... 92
5.5.3.2. DSI_RX_STATE_INT_MASK (0x01A4) ......................................................................................................................... 93
5.5.3.3. DSI_RXTRIG_INT_STAT (0x01A8)............................................................................................................................... 94
5.5.3.4. DSI_RXTRIG_INT_MASK (0x01AC) ............................................................................................................................. 95
5.5.3.5. DSITX_INTERNAL_STAT (0x01B0).............................................................................................................................. 96
5.5.3.6. DSI_ACKERROR (0x01B4)........................................................................................................................................... 97
5.5.3.7. DSI_RXFIFO (0x01B8) .................................................................................................................................................. 97
5.5.3.8. DSI_RX_HEADER (0x01BC) ........................................................................................................................................ 98
5.5.3.9. DSI_LPRX_THRESH_COUNT (0x01C0) ...................................................................................................................... 98
5.5.3.10. DSI_LPRX_FIFO_LEVEL (0x01C4) ............................................................................................................................ 99
Error Experience Registers ...................................................................................................................................... 100 5.5.4.
5.5.4.1. DSI_PRTO_INT_STAT (0x0208) ................................................................................................................................ 100
5.5.4.2. DSI_PRTO_INT_MASK (0x020C) ............................................................................................................................... 100
5.5.4.3. APP_SIDE_ERR_INT_STAT (0x0210) ....................................................................................................................... 101
5.5.4.4. APP_SIDE_ERR_INT_MASK (0x0214) ...................................................................................................................... 102
5.5.4.5. DSI_RX_ERR_INT_STAT (0x0218) ............................................................................................................................ 103
5.5.4.6. DSI_RX_ERR_INT_MASK (0x021C) .......................................................................................................................... 104
DSI LPTX Registers ................................................................................................................................................. 105 5.5.5.
5.5.5.1. DSI_LPTX_INT_STAT (0x0220) ................................................................................................................................. 105
5.5.5.2. DSI_LPTX_INT_MASK (0x0224) ................................................................................................................................ 106
