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3132;Serial

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Data Sheet

SiI3132 PCI Express to Serial ATA Controller

Data Sheet

Document # SiI-DS-0138-E

SiI3132 PCI Express to Serial ATA Controller

Data Sheet

Silicon Image, Inc.

May, 2010

information (including trade secrets, copyright, and other interests) of Silicon Image, Inc. You may not use these

materials except only for your bona fide non-commercial evaluation of your potential purchase of products and/or

services from Silicon Image or its affiliates, and/or only in connection with your purchase of products and/or services

from Silicon Image or its affiliates, and only in accordance with the terms and conditions herein. You have no right to

copy, modify, transfer, sublicense, publicly display, create derivative works of or distribute these materials, or otherwise

make these materials available, in whole or in part, to any third party.

Patents

The subject

matter described herein contains one or more inventions claimed in patents and/or patents pending owned by

Silicon Image, Inc., including but not limited to the inventions claimed in US patents #6,914,637, #6,151,334,

#6,026,124, #5,974,464 and #5,825,824.

Trademark Acknowledgment

Silico

n Image™, VastLane™, SteelVine™, PinnaClear™, Simplay™, Simplay HD™, Satalink™, InstaPort™, and

TMDS™ are trademarks or registered trademarks of Silicon Image, Inc. in the United States and other countries.

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Further Information

o request other materials, documentation, and information, contact your local Silicon Image, Inc. sales office or visit

the Silicon Image, Inc. web site at www.siliconimage.com

Revision History

Revision Date Comment

A 4/8/2005 Derived from preliminary datasheet rev 0.3

A01 8/15/2005 Updated register description for BAR0 Offset 50

A02 8/11/2006 Corrected inconsistent sentences (minor fixes including mistyping)

C 2/2/2007 Removed confidential markings (no longer under NDA); updated Marking Specification.

D 2/23/2007 Changes to package drawing. New formatting applied.

E 5/7/2010 Added I

C section; rewrote Initialization Sequence section; copyedited and brought to current standards.

SiI3132 PCI Express to Serial ATA Controller

Data Sheet

Silicon Image, Inc.

Table of Contents

Overview ..............................................................................................................................................................................1

Features ............................................................................................................................................................................1

Overall Features............................................................................................................................................................1

PCI Express Features....................................................................................................................................................1

Serial ATA Features ...................................................................................................................................................... 1

Pin Diagram......................................................................................................................................................................2

Electrical Characteristics ......................................................................................................................................................3

Electrical Characteristics ..................................................................................................................................................3

SATA Interface Timing Specifications .............................................................................................................................5

SATA Interface Transmitter Output Jitter Characteristics ................................................................................................5

PCI Express Interface Timing Specifications...................................................................................................................6

PCI Express Interface Transmitter Output Jitter Characteristics ......................................................................................6

CLKI SATA Reference Clock Input Requirement............................................................................................................ 6

Power Supply Noise Requirements ..................................................................................................................................6

Pin Descriptions....................................................................................................................................................................7

PCI Express Pins .............................................................................................................................................................. 7

Flash Data and Address Pins ............................................................................................................................................7

FLSAH Control, I

C, and LED Pins.................................................................................................................................8

Serial ATA Pins.................................................................................................................................................................8

Test Pins............................................................................................................................................................................ 8

Power/Ground Pins........................................................................................................................................................... 9

Pin List by Pin Number ..................................................................................................................................................10

Package Drawing................................................................................................................................................................ 11

Marking Specification ....................................................................................................................................................12

Ordering Information......................................................................................................................................................12

Programming Model........................................................................................................................................................... 13

SiI3132 Block Diagram.................................................................................................................................................. 13

SiI3132 SATA Port Block Diagram................................................................................................................................ 14

Direct Command Transfer Method – Host controlled write to Slot............................................................................15

Indirect Command Transfer Method – SiI3132 controlled command transfer........................................................... 15

Data Structures ............................................................................................................................................................... 16

The Command Slot.....................................................................................................................................................16

The Scatter/Gather Entry (SGE).................................................................................................................................16

The Scatter/Gather Table (SGT)................................................................................................................................. 16

The Port Request Block (PRB)................................................................................................................................... 17

The PRB Control Field............................................................................................................................................... 18

The PRB Protocol Override Field ..............................................................................................................................19

Standard ATA Command PRB Structure ....................................................................................................................19

PACKET Command PRB Structure ...........................................................................................................................21

Soft Reset PRB Structure ...........................................................................................................................................22

External Command PRB Structure............................................................................................................................. 22

Interlocked Receive PRB Structure............................................................................................................................ 23

Operation ........................................................................................................................................................................24

Methods to Issue Commands......................................................................................................................................24

Reset and Initialization ............................................................................................................................................... 24

PERST# Reset ........................................................................................................................................................24

Global Reset ........................................................................................................................................................... 25

Port Reset ...............................................................................................................................................................25

Device Reset...........................................................................................................................................................25

Port Initialize ..........................................................................................................................................................25

Port Ready .............................................................................................................................................................. 25

Port Reset Operation................................................................................................................................................... 25

Initialization Sequence ...............................................................................................................................................25

SiI3132 PCI Express to Serial ATA Controller

Data Sheet

Silicon Image, Inc.

Initialize Port and Retrieve Device Signature ........................................................................................................26

Port Multiplier Enumeration Procedure..................................................................................................................26

ATAPI PACKET Device Procedure .......................................................................................................................26

Disk Drive Procedure .............................................................................................................................................27

Interrupts and Command Completion ........................................................................................................................27

Interrupt Sources ........................................................................................................................................................27

Command Completion — The Slot Status Registers..................................................................................................30

The Attention Bit ........................................................................................................................................................31

Interrupt Service Procedure........................................................................................................................................ 31

Interrupt No Clear on Read ........................................................................................................................................31

Error Processing .........................................................................................................................................................31

Error Recovery Procedures......................................................................................................................................... 32

Auto-Initialization ..............................................................................................................................................................34

Auto-Initialization from Flash........................................................................................................................................34

Auto-Initialization from EEPROM.................................................................................................................................35

Register Definitions............................................................................................................................................................37

PCI Configuration Space................................................................................................................................................ 37

Device ID – Vendor ID...............................................................................................................................................38

PCI Status – PCI Command .......................................................................................................................................38

PCI Class Code – Revision ID ...................................................................................................................................39

BIST – Header Type – Latency Timer – Cache Line Size..........................................................................................39

Base Address Register 0 .............................................................................................................................................39

Base Address Register 1 .............................................................................................................................................40

Base Address Register 2 .............................................................................................................................................40

Subsystem ID — Subsystem Vendor ID..................................................................................................................... 40

Expansion ROM Base Address ..................................................................................................................................41

Capabilities Pointer ....................................................................................................................................................41

Max Latency – Min Grant – Interrupt Pin – Interrupt Line........................................................................................41

Header Write Enable................................................................................................................................................... 42

Power Management Capability...................................................................................................................................42

Power Management Control + Status .........................................................................................................................43

MSI Capability ........................................................................................................................................................... 43

Message Address ........................................................................................................................................................ 44

MSI Message Data .....................................................................................................................................................44

PCI Express Capability............................................................................................................................................... 44

Device Capabilities..................................................................................................................................................... 45

Device Status and Control .......................................................................................................................................... 45

Link Capabilities ........................................................................................................................................................46

Link Status and Control..............................................................................................................................................46

Global Register Offset................................................................................................................................................ 47

Global Register Data ..................................................................................................................................................47

Port Register Offset ....................................................................................................................................................47

Port Register Data....................................................................................................................................................... 47

Advanced Error Reporting Capability........................................................................................................................ 48

Uncorrectable Error Status .........................................................................................................................................48

Uncorrectable Error Mask .......................................................................................................................................... 49

Uncorrectable Error Severity......................................................................................................................................49

Correctable Error Status .............................................................................................................................................49

Correctable Error Mask .............................................................................................................................................. 50

Advanced Error Capabilities and Control ..................................................................................................................50

Header Log ................................................................................................................................................................. 51

Internal Register Space – Base Address 0 ...................................................................................................................... 51

Global Port Slot Status ...............................................................................................................................................52

Global Control............................................................................................................................................................52

Global Interrupt Status................................................................................................................................................53

PHY Configuration..................................................................................................................................................... 53

SiI3132 PCI Express to Serial ATA Controller

Data Sheet

Silicon Image, Inc.

BIST Control .............................................................................................................................................................. 54

BIST Pattern ...............................................................................................................................................................54

BIST Status.................................................................................................................................................................54

C Control..................................................................................................................................................................55

C Status.................................................................................................................................................................... 56

C Slave Address ....................................................................................................................................................... 56

C Data Buffer........................................................................................................................................................... 57

Flash Address ............................................................................................................................................................. 57

Flash Memory Data / GPIO Control........................................................................................................................... 57

Internal Register Space – Base Address 1 .................................................................................................................. 58

Port LRAM................................................................................................................................................................. 59

Port Slot Status ........................................................................................................................................................... 59

Port Control Set ..........................................................................................................................................................60

Port Status...................................................................................................................................................................61

Port Control Clear....................................................................................................................................................... 61

Port Interrupt Status....................................................................................................................................................62

Port Interrupt Enable Set / Port Interrupt Enable Clear.............................................................................................. 63

32-bit Activation Upper Address ................................................................................................................................ 63

Port Command Execution FIFO ................................................................................................................................. 63

Port Command Error ..................................................................................................................................................63

Port FIS Configuration ...............................................................................................................................................65

Port PCI Express Request FIFO Threshold................................................................................................................ 65

Port 8B/10B Decode Error Counter ...........................................................................................................................66

Port CRC Error Counter ............................................................................................................................................. 66

Port Handshake Error Counter ................................................................................................................................... 67

Port PHY Configuration .............................................................................................................................................67

Port Device Status ...................................................................................................................................................... 68

Port Device QActive...................................................................................................................................................68

Port Context................................................................................................................................................................ 69

SControl......................................................................................................................................................................69

SStatus ........................................................................................................................................................................ 70

SError ......................................................................................................................................................................... 71

SActive ....................................................................................................................................................................... 71

SNotification...............................................................................................................................................................72

Internal Register Space – Base Address 2 ...................................................................................................................... 72

Global Register Offset................................................................................................................................................ 72

Global Register Data ..................................................................................................................................................72

Port Register Offset ....................................................................................................................................................73

Port Register Data....................................................................................................................................................... 73

Power Management............................................................................................................................................................74

Flash, GPIO, EEPROM, and I

C Programming ................................................................................................................. 75

Flash Memory Access..................................................................................................................................................... 75

PCI Direct Access....................................................................................................................................................... 75

Register Access........................................................................................................................................................... 75

Flash Write Operation............................................................................................................................................. 75

Flash Read Operation .............................................................................................................................................75

C Operation.................................................................................................................................................................. 75

C Master Write Operation........................................................................................................................................ 76

C Master Read Operation......................................................................................................................................... 76

Setup for a Read Operation ....................................................................................................................................76

Read the Data .........................................................................................................................................................77

C Slave Read Operations .........................................................................................................................................77

Standards Documents ......................................................................................................................................................... 78