简易数字频率计vhdl（自动档）

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity corna is port(clr,sig,door:in std_logic; alm:out std_logic; q3,q2,q1,q0,dang:out std_logic_vector(3 downto 0)); end corna; architecture corn_arc of corna is begin process(door,sig) variable c0,c1,c2,c3,c4,c5,c6,c7,c8:std_logic_vector(3 downto 0); variable x:std_logic; begin if sig'event and sig='1'then if door='1'then if c0<"1001"then c0:=c0+1; else c0:="0000"; if c1<"1001"then c1:=c1+1; else c1:="0000"; if c2<"1001"then c2:=c2+1; else c2:="0000"; if c3<"1001"then c3:=c3+1; else c3:="0000"; if c4<"1001"then c4:=c4+1; else c4:="0000"; if c5<"1001"then c5:=c5+1; else c5:="0000"; if c6<"1001"then c6:=c6+1; else c6:="0000"; if c7<"1001"then c7:=c7+1; else c7:="0000"; if c8<"1001"then c8:=c8+1; else c8:="0000"; alm<='1'; end if; end if; end if; end if; end if; end if; end if; end if; end if; else if clr='0'then alm<='0'; end if; c8:="0000";--mh c7:="0000";--mh c6:="0000";--mh c5:="0000";--kh c4:="0000";--kh c3:="0000";--kh c2:="0000";--h c1:="0000";--h c0:="0000";--h end if; if c8/="0000"then q3<="0000"; q2<=c8; q1<=c7; q0<=c6; dang<="0011"; elsif c7/="0000"then q3<="0000"; q2<=c8; q1<=c7; q0<=c6; dang<="0011"; elsif c6/="0000"then q3<=c6; q2<=c5; q1<=c4; q0<=c3; dang<="0011"; elsif c5/="0000"then q3<="0000"; q2<=c5; q1<=c4; q0<=c3; dang<="0010"; elsif c4/="0000"then q3<=c4; q2<=c3; q1<=c2; q0<=c1; dang<="0010"; elsif c3/="0000"then q3<=c3; q2<=c2; q1<=c1; q0<=c0; dang<="0010"; else q3<="0000"; q2<=c2; q1<=c1; q0<=c0; dang<="0001"; end if; end if; end process; end corn_arc;