ZYNQ AXI总线PL/PS间通信的例程代码

Language File-Name IP Library File-Path Verilog, processing_system7_bfm_v2_0_arb_wr.v, system, xil_defaultlib, ../../../ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_arb_wr.v Verilog, processing_system7_bfm_v2_0_arb_rd.v, system, xil_defaultlib, ../../../ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_arb_rd.v Verilog, processing_system7_bfm_v2_0_arb_wr_4.v, system, xil_defaultlib, ../../../ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_arb_wr_4.v Verilog, processing_system7_bfm_v2_0_arb_rd_4.v, system, xil_defaultlib, ../../../ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_arb_rd_4.v Verilog, processing_system7_bfm_v2_0_arb_hp2_3.v, system, xil_defaultlib, ../../../ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_arb_hp2_3.v Verilog, processing_system7_bfm_v2_0_arb_hp0_1.v, system, xil_defaultlib, ../../../ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_arb_hp0_1.v Verilog, processing_system7_bfm_v2_0_ssw_hp.v, system, xil_defaultlib, ../../../ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_ssw_hp.v Verilog, processing_system7_bfm_v2_0_sparse_mem.v, system, xil_defaultlib, ../../../ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_sparse_mem.v Verilog, processing_system7_bfm_v2_0_reg_map.v, system, xil_defaultlib, ../../../ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_reg_map.v Verilog, processing_system7_bfm_v2_0_ocm_mem.v, system, xil_defaultlib, ../../../ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_ocm_mem.v Verilog, processing_system7_bfm_v2_0_intr_wr_mem.v, system, xil_defaultlib, ../../../ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_intr_wr_mem.v Verilog, processing_system7_bfm_v2_0_intr_rd_mem.v, system, xil_defaultlib, ../../../ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_intr_rd_mem.v Verilog, processing_system7_bfm_v2_0_fmsw_gp.v, system, xil_defaultlib, ../../../ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_fmsw_gp.v Verilog, processing_system7_bfm_v2_0_regc.v, system, xil_defaultlib, ../../../ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_regc.v Verilog, processing_system7_bfm_v2_0_ocmc.v, system, xil_defaultlib, ../../../ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_ocmc.v Verilog, processing_system7_bfm_v2_0_interconnect_model.v, system, xil_defaultlib, ../../../ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_interconnect_model.v Verilog, processing_system7_bfm_v2_0_gen_reset.v, system, xil_defaultlib, ../../../ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_gen_reset.v Verilog, processing_system7_bfm_v2_0_gen_clock.v, system, xil_defaultlib, ../../../ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_gen_clock.v Verilog, processing_system7_bfm_v2_0_ddrc.v, system, xil_defaultlib, ../../../ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_ddrc.v Verilog, processing_system7_bfm_v2_0_axi_slave.v, system, xil_defaultlib, ../../../ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_axi_slave.v Verilog, processing_system7_bfm_v2_0_axi_master.v, system, xil_defaultlib, ../../../ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_axi_master.v Verilog, processing_system7_bfm_v2_0_afi_slave.v, system, xil_defaultlib, ../../../ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_afi_slave.v Verilog, processing_system7_bfm_v2_0_processing_system7_bfm.v, system, xil_defaultlib, ../../../ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_processing_system7_bfm.v Verilog, system_processing_system7_0_0.v, system, xil_defaultlib, ../../../bd/system/ip/system_processing_system7_0_0/sim/system_processing_system7_0_0.v Verilog, myip_axi_lite_v1_0_S00_AXI.v, system, xil_defaultlib, ../../../bd/system/ipshared/xilinx.com/myip_axi_lite_v1_0/hdl/myip_axi_lite_v1_0_S00_AXI.v Verilog, myip_axi_lite_v1_0.v, system, xil_defaultlib, ../../../bd/system/ipshared/xilinx.com/myip_axi_lite_v1_0/hdl/myip_axi_lite_v1_0.v Verilog, system_myip_axi_lite_0_0.v, system, xil_defaultlib, ../../../bd/system/ip/system_myip_axi_lite_0_0/sim/system_myip_axi_lite_0_0.v VHDL, cdc_sync.vhd, system, lib_cdc_v1_0_2, ../../../ipstatic/lib_cdc_v1_0/hdl/src/vhdl/cdc_sync.vhd VHDL, upcnt_n.vhd, system, proc_sys_reset_v5_0_8, ../../../ipstatic/proc_sys_reset_v5_0/hdl/src/vhdl/upcnt_n.vhd VHDL, sequence_psr.vhd, system, proc_sys_reset_v5_0_8, ../../../ipstatic/proc_sys_reset_v5_0/hdl/src/vhdl/sequence_psr.vhd VHDL, lpf.vhd, system, proc_sys_reset_v5_0_8, ../../../ipstatic/proc_sys_reset_v5_0/hdl/src/vhdl/lpf.vhd VHDL, proc_sys_reset.vhd, system, proc_sys_reset_v5_0_8, ../../../ipstatic/proc_sys_reset_v5_0/hdl/src/vhdl/proc_sys_reset.vhd VHDL, system_rst_processing_system7_0_100M_0.vhd, system, xil_defaultlib, ../../../bd/system/ip/system_rst_processing_system7_0_100M_0/sim/system_rst_processing_system7_0_100M_0.vhd Verilog, generic_baseblocks_v2_1_carry_and.v, system, generic_baseblocks_v2_1_0, ../../../ipstatic/generic_baseblocks_v2_1/hdl/verilog/generic_baseblocks_v2_1_carry_and.v Verilog, generic_baseblocks_v2_1_carry_latch_and.v, system, generic_baseblocks_v2_1_0, ../../../ipstatic/generic_baseblocks_v2_1/hdl/verilog/generic_baseblocks_v2_1_carry_latch_and.v Verilog, generic_baseblocks_v2_1_carry_latch_or.v, system, generic_baseblocks_v2_1_0, ../../../ipstatic/generic_baseblocks_v2_1/hdl/verilog/generic_baseblocks_v2_1_carry_latch_or.v Verilog, generic_baseblocks_v2_1_carry_or.v, system, generic_base