推荐一篇好文章:关于利用perl 脚本产生状态机的verilog代码和DC 脚本的
需积分: 50 137 浏览量
2019-08-27
22:01:12
上传
评论 1
收藏 78KB PDF 举报
fsm_perl: A Script to Generate RTL Code for State
Machines and Synopsys Synthesis Scripts
Clifford E. Cummings
Sunburst Design, Inc.
ABSTRACT
Coding a Verilog RTL model of a state machine requires significant effort to generate an
efficient synthesizable implementation. There are a number of different coding styles that can
yield different results with varying degrees of efficiency. Because of the effort required to code a
Verilog state machine, an engineer typically makes a guess as to which coding style will yield a
good implementation and then rarely experiments with other styles after the first model simulates
correctly.
This paper details a new and highly abbreviated language for coding a state machine and then
describes the use of a Perl script called fsm_perl to turn the abbreviated code into a variety of
synthesizable models for synthesis experimentation.
The fsm_perl also generates an accompanying dc_shell script to synthesize and compare the area
and timing of each synthesized implementation.
剩余19页未读，继续阅读
资源评论
drjiachen
- 粉丝: 168
- 资源: 2144
