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AD9371_Design_File.zip （40个子文件）

AD9371_Design_File_Package

AD9371-User-Guide-UG-992.pdf 12.02MB

ad9371_IBIS_AMI.zip 3.32MB

Imported ADRV9371-N_PCBZ_Layout_RevB.PrjPcb

ADRV9371-N_PCBZ_Layout_RevB.PrjPcb 40KB

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allegro.jrl 7KB

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ADRV9371-W_Layout_RevB.LOG 2KB

ADRV9371-W_Layout_RevB.PcbDoc 35.62MB

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ADRV9371-W_Schematic_RevB.pdf 148KB

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AD9371_s-parameter_models.zip 32KB

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System Development User Guide

UG-992

One Technology Way • P. O. Box 9106 • Norwood, MA 02062-9106, U.S.A. • Tel: 781.329.4700 • Fax: 781.461.3113 • www.analog.com

System Development User Guide for the AD9371 Integrated,

Dual RF Transceiver with Observation Path

PLEASE SEE THE LAST PAGE FOR AN IMPORTANT

WARNING AND LEGAL TERMS AND CONDITIONS.

Rev. A | Page 1 of 307

INTRODUCTION

This user guide is the main source of information for systems

engineers and software developers using the AD9371 software

defined radio transceiver. The sections in this user guide are

organized to make it easier for users to find the information

pertinent to their area of interest. These sections are as folllows:

• System Overview. This section explains the capability of

the device and serves as an introduction to all the subsystems

and functions, including the block diagrams and interfaces.

• System Architecture Description. This section explains the

software design approach using the application

programming interface (API) and all details required to

develop code on the device.

• Software Integration. This section describes the process for

developing code using the AD9371 APIs. This section lists

common API functions for user integration into the code

base.

• Serial Peripheral Interface (SPI). The SPI is the main

control interface between the baseband processor (BBP)

and the integrated transceiver.

• JESD204B Interface. This section provides a description of

the JESD204B digital interface, setup, and configuration

options.

• System Initialization. This section provides the sequence of

steps required at startup.

• Quadrature Error Correction, Calibration, and ARM

Configuration. This section describes the calibration and

error correction functions and setup guidelines for

configuring the ARM processor to perform scheduled

adjustments.

• System Control. This section describes the commands and

sequences for setting up the different radio channels.

• Tx Power Control. This section explains the commands

and procedures for adjusting Tx power control during

normal operation.

• Reference Clock and SYSREF Connections. This section

describes how to set up the reference clocks needed for all

internal clock and signal generation as well as data

synchronization.

• Synthesizer Configuration. This section describes how to

configure the synthesizers for different modes of operation.

This section includes details for receiver (Rx), transmitter

(Tx), observation receiver (ORx), and clock phase-locked

loop (PLL) setup, as well as the calibration PLL setup.

• Gain Control. This section describes the options for

controlling receiver gain settings, including manual gain

control (MGC) provided by the BBP and automatic gain

control (AGC) provided by the integrated transceiver.

• Filter Configuration. This section describes all the digital

filter blocks in the the receivers and transmitters, and explains

the programmable FIR filters and how to set their coefficients.

• Observation Receiver. This section describes the ORx inputs

and the sniffer receiver (SnRx) inputs, including system

implementation and setup APIs.

• TDD Configuration and Setup. This section describes

software configuration to operate in a time division

duplexed (TDD) system.

• General-Purpose Input/Output (GPIO) Configuration.

This section describes the options for configuring standard

digital GPIO pins.

• 3.3 V General-Purpose Input/Output Overview. This

section describes the options for configuring the 3.3 V

supplied GPIO pins.

• General-Purpose Interrupt Overview. This section describes

setup and operation of the general-purpose interrupt pin.

• Auxilliary Converters—AUXDAC_x, AUXADC. This

section describes the capability of the AUXADC_x inputs,

the AUXDAC_x outputs, and how to properly configure

the inputs and outputs for various applications.

• RF Port Interface. This section explains all the details

necessary to properly match the RF impedances of each

differential input and output port.

• Printed Circuit Board Layout Guidelines. This section

describes the printed circuit board (PCB) construction,

layout, routing, and isolation techniques necessary to

optimize

AD9371 performance.

• Power Management Considerations. This section describes

the power supply design and all the considerations needed

to optimize AD9371 performance.

• AD9371 Demonstration System Overview. This section

describes the AD9371 demonstration system, including the

evaluation board, motherboard, and hardware integration

setup needed to properly evaluate device performance.

• AD9371 Transceiver Evaluation Software (TES). This

section describes the AD9371 transceiver evaluation

software (TES) that provides a graphical user interface that

controls the evaluation system.

UG-992 System Development User Guide

Rev. A | Page 2 of 307

TABLE OF CONTENTS

Introduction ...................................................................................... 1

Revision History ............................................................................... 3

System Overview .............................................................................. 5

System Architecture Description .................................................... 7

Software Architecture .................................................................. 7

Folder Structure ............................................................................ 8

Software Integration ......................................................................... 9

Modifying common.c .................................................................. 9

Developing the Application ...................................................... 10

Serial Peripheral Interface (SPI) ................................................... 13

SPI Configuration Using API Function .................................. 13

SPI Bus Signals ............................................................................ 13

SPI Data Transfer Protocol ........................................................ 14

Timing Diagrams ........................................................................ 15

JESD204B Interface ........................................................................ 17

Receivers (ADC) Datapath ........................................................ 18

Transmitters (DAC) Datapath .................................................. 38

Link Establishment ..................................................................... 52

Hardware Considerations for SYNC Signals .......................... 53

Compatibility with Xilinx JESD204B FPGA IP ..................... 53

Multichip Synchronization ........................................................ 53

Multichip API Function Description ....................................... 55

System Initialization ....................................................................... 56

Modification of common.c for User Code Integration ......... 56

Data Structure Member Initialization ..................................... 56

Initialization Sequence............................................................... 58

Example Code ............................................................................. 58

Source Code Examples .............................................................. 59

Quadrature Error Correction, Calibration, and ARM

Configuration .................................................................................. 78

ARM State Machine Overview ................................................. 78

Loading the ARM ....................................................................... 78

Initial ARM Calibrations ........................................................... 78

Tracking Calibrations ................................................................. 80

Tracking Calibration Scheduler ................................................ 80

System Considerations for ARM Calibrations ....................... 83

ARM GPIOs ................................................................................ 91

Initial Calibration Errors ........................................................... 92

Tracking Calibration Errors ...................................................... 94

Reading the ARM Version ........................................................ 94

Performing an ARM Memory Dump ...................................... 94

System Control................................................................................ 97

Control of Signal Chains (Tx/Rx) ............................................ 97

ORx Path Control ....................................................................... 99

ARM GPIO Operation ............................................................ 102

Tx Power Control ......................................................................... 103

Reference Clock and SYSREF Connections .............................. 104

Connections for External Clock (DEV_CLK_IN) ............... 104

DEV_CLK Phase Noise Requirements .................................. 104

SYSREF Requirements ............................................................. 105

Synthesizer Configuration........................................................... 107

Connections for External LO ................................................. 108

Software Configuration ........................................................... 110

RF PLL Frequency Change Procedure .................................. 112

RF PLL Resolution Limitations .............................................. 118

Gain Control ................................................................................. 119

Receiver Datapath—Variable Gain Elements ........................... 119

Gain Table Format .................................................................... 120

Gain Table Programming Description .................................. 122

Rx Gain Delay ........................................................................... 123

Manual Gain Control, Hybrid Mode, and Automatic Gain

Control Overview ..................................................................... 124

Manual Gain Control ............................................................... 124

Hybrid Gain Control................................................................ 126

Automatic Gain Control .......................................................... 126

AGC API Commands .............................................................. 132

API Programming Summary .................................................. 134

Summary of the AGC Parameters .......................................... 144

Digital Gain Compensation, Slicer, and Floating Point

Formatter ................................................................................... 145

Slicer API Commands and GPIO Information .................... 149

Floating Point API Commands .............................................. 151

Filter Configuration ..................................................................... 153

Receiver Signal Path ................................................................. 153

Rx Signal Path Example ........................................................... 155

Transmitter Signal Path ........................................................... 157

Tx Signal Path Example ........................................................... 157

Observation Receivers Signal Path ........................................ 158

Observation Receiver Signal Path Example .......................... 160

API Data Structures and API Commands ............................ 161

System Development User Guide UG-992

Rev. A | Page 3 of 307

Observation Receiver (ORx) ....................................................... 162

Observation System Receiver Details .................................... 163

ORx Automatic, Hybrid, and Manual Gain Control ........... 165

Observation System Receiver Front-End Programming ....... 166

TDD Configuration and Setup ................................................... 168

TDD in the Mykonos Evaluation System ............................. 168

API/DLL Commands for TDD Configuration .................... 180

General-Purpose Input/Output (GPIO) Configuration ......... 184

GPIO Operation ....................................................................... 185

GPIO Manual Mode ................................................................ 189

Monitor Output ........................................................................ 191

ARM GPIO Interface ............................................................... 197

Tx Attenuation Control ........................................................... 201

Secondary SErial Peripheral Interface (SPI2) ........................... 204

Rx Manual Gain Control ......................................................... 206

3.3 V General-Purpose Input/Output Overview ..................... 209

3.3 V General-Purpose Input/Output control ..................... 211

General-Purpose Interrupt Overview ....................................... 213

Auxilliary Converters—AUXDAC_x, AUXADC_x, and

Temperature Sensor ..................................................................... 215

Auxiliary DACs ........................................................................ 215

Auxiliary ADC .......................................................................... 217

Temperature Sensor ................................................................. 219

RF Port Interface .......................................................................... 223

Series and Parallel Impedance Models .................................. 224

RF Port Impedance Data ......................................................... 225

Transmitter Bias and Port Interface ....................................... 233

General Receiver Path Interface ............................................. 234

Impedance Matching Network ............................................... 237

Board Layout Design Recommendations ............................. 243

Printed Circuit Board Layout Guidelines .................................. 244

PCB Material and Stack Up Selection .................................... 244

Fanout and Trace Space Guidelines ........................................ 246

Component Placement and Routing Priorities ..................... 247

RF and JESD204B Transmission Line Layout ....................... 252

Isolation Techniques Used on the ADRV9371-N/PCBZ

Evaluation Card ......................................................................... 259

Unused Pins ............................................................................... 262

Power Management Considerations ........................................... 263

Power Supply Sequence ............................................................ 263

Power Distribution For Different Power Supply Domains . 263

ADRV9371-N/PCBZ Evaluation Card Power Supply Block

Diagram ...................................................................................... 265

RF and Clock Synthesizer Supplies......................................... 266

AD9371 Demonstration System Overview ............................... 267

Initial Setup ................................................................................ 267

Hardware and Software Requirements .................................. 267

Hardware Setup for External Tx Local Oscillator (LO)

Leakage Calibration .................................................................. 270

Hardware Operation ................................................................. 271

AD9371 Transceiver Evaluation Software (TES) ...................... 273

Installation ................................................................................. 273

Starting the AD9371 Transceiver Evaluation Software ........ 273

Normal Operation .................................................................... 275

Configuring the AD9371 ......................................................... 276

Programming the Evaluation System ..................................... 288

Other TES Features ................................................................... 289

Receiver Setup ........................................................................... 293

Transmitter Setup ...................................................................... 296

TDD Mode ................................................................................. 298

Scripting ..................................................................................... 303

REVISION HISTORY

1/2017—Rev. 0 to Rev. A

Changes to Introduction Section .................................................... 1

Deleted /src/example Section .......................................................... 7

Changes to Figure 3........................................................................... 8

Changes to Developing the Application Section ......................... 10

Changes to API Sequence Section ................................................ 11

Changes to Figure 4 and Figure 5 .................................................. 15

Change to t

Parameter, Table 4 and Figure 6 ........................... 16

Changes to Table 38 ........................................................................ 38

Added Hardware Considerations for Sync Signals Section ....... 53

Changes to Data Structure Member Initialization Section........ 56

Deleted Folder Location Section and Figure 28;

Renumbered Sequentially .............................................................. 58

Changes to headless.c Section ....................................................... 58

Added Reference Clock and SYSREF Connections Section,

Connections for External Clock (DEV_CLK_IN) Section,

Figure 47, DEV_CLK Phase Noise Requirements Section,

Table 92, and Table 93; Renumbered Sequentially ................... 104

Added SYSREF Requirements Section and Figure 48 .............. 105

Aded Minimum Delay Requirements Between SYSREF Pulses

Section, Timing of SYSREF Compared to DEV_CLK Section,

Figure 50, and Figure 51 ............................................................... 106

UG-992 System Development User Guide

Rev. A | Page 4 of 307

Added Connections for External LO Section, Figure 52, and

Table 94 .......................................................................................... 107

Added Performance Limitations Section and Figure 53 ......... 109

Changes to Example 1 Section, Example 2 Section, and

Example 3 Section ........................................................................ 118

Deleted DEV_CLK, SYSREF, and External LO Section,

Overview Section, Connections for the External Clock

(DEV_CLK_IN) Section, Figure 51, and Figure 52; ................ 120

Deleted DEV_CLK Phase Noise Requirements Section,

Figure 53, Table 94, and Table 95; Renumbered Sequentially ....... 121

Deleted Figure 54 and Figure 55 ................................................. 122

Deleted Multichip Synchronization (JESD204B Mode) Section

and Figure 56 ................................................................................. 123

Deleted Connections for External LO Section, Figure 57, and

Table 96 .......................................................................................... 124

Changes to Analog Peak Detector (APD) Basics Section ....... 127

Changes to Half-Band 2 (HB2) Overload Detector

Basics Section ................................................................................ 129

Added TDD Configuration and Setup Section, TDD in the

Mykonos Evaluation System Section, ARM Input and Output

Signals Section, and ARM Pin Mode Configurations Section ...... 168

Added Figure 88 ............................................................................ 169

Added ARM Acknowledge Signals Section, Table 133, and

Figure 89 ........................................................................................ 170

Added Table 134 and Table 135 .................................................. 171

Added Figure 90 and Table 136 .................................................. 172

Added FPGA Output Signals Section, Data Path Trigger

Modes Section, and Table 137 ..................................................... 173

Added Table 138 ........................................................................... 174

Added TDD Finite State Machine Class Section, Quick Help for

Programming FPGA/Mykonos Section, and Table 139 .......... 175

Added ORX_MODE[2:0] and ORX_TRIGGER, as Seen by

the FPGA Section and Example TDD Script in IronPython

Section ............................................................................................ 176

Added API/DLL Commands for TDD Configuration Section .... 180

Added Secondary Serial Peripheral Interface (SPI2) Section,

Figure 97, and Figure 98 .............................................................. 204

Added Table 160, SPI2 Register Map Section, API Description

Section, and Table 161 ................................................................. 205

Moved Impedance Matching Network Section ........................ 237

Moved Figure 144 to Figure 146 ................................................. 238

Moved Figure 147 to Figure 149 ................................................. 239

Moved Figure 150 ......................................................................... 240

Moved Selected Balun and Component Values Section, and

Table 169 to Table 172 .................................................................. 241

Moved Table 173 to Table 176 and Mykonos Tx1 and TX2 Port

Impedance Section ....................................................................... 242

Moved Figure 151 and Figure 152 .............................................. 243

Added Board Layout Design Recommendations Section ....... 243

Added Printed Circuit Board Layout Guidelines Section and

PCB Material and Stack Up Selection Section.......................... 244

Added Figure 153 and Table 177 ................................................ 245

Added Fanout and Trace Space Guidelines Section and

Figure 154 ...................................................................................... 246

Added Component Placement and Routing Priorities Section,

Signals with Highest Routing Priority Section, and Figure 155 .. 247

Added Figure 156 ......................................................................... 248

Added Signals with Second Routing Priority Section and

Figure 157 ...................................................................................... 249

Added Figure 158 and Figure 159 .............................................. 250

Added Signals with Lowest Routing Priority and Figure 160 ....... 251

Added RF and JESD204B Transmission Line Layout Section ...... 252

Changes to Table 178 to Table 181 ............................................. 253

Changes to Example 5 Section, Table 182, and RF Line Design

Summary Section ......................................................................... 254

Added Figure 161 and Figure 162 .............................................. 254

Added Transmitter Bias and Port Interface Section, Figure 163,

Figure 164, and Tx Balun DC Supply Options Section ........... 255

Added Figure 165, DC Balun Section, and Chokes Section ... 256

Added Figure 166 ......................................................................... 257

Added Figure 167, Figure 168, JESD204B Trace Routing

Recommendations Section, and Routing Recommendations

Section ............................................................................................ 258

Added Stripline vs. Microstrip Section, Isolation Techniques

Used on the ADRV9371-N/PCBZ Evaluation Card Section, and

Figure 169 ...................................................................................... 259

Added Figure 170 ......................................................................... 260

Added Isolation Between JESD204B Lines Section and

Figure 171 ...................................................................................... 261

Added Unused Pins Section and Table 183 .............................. 262

Added Power Management Considerations Section and

Table 184 ........................................................................................ 263

Added ADRV9371-N/PCBZ Evaluation Card Power Supply

Block Diagram Section and Figure 173 ..................................... 265

Added RF and Clock Synthesizer Supplies Section ................. 266

Changes to Figure 202 and AD9528 Description Section ...... 286

Changes to Figure 213 ................................................................. 291

7/2016—Revision 0: Initial Version

System Development User Guide UG-992

Rev. A | Page 5 of 307

SYSTEM OVERVIEW

Analog Devices, Inc., provides a variety of highly integrated RF

agile transceivers, including the AD9371. This transceiver family

provides dual-channel receivers, dual-channel transmitters,

integrated synthesizers, digital signal processing functions, and

a high speed serial interface. The devices operate over the wide

frequency range of 300 MHz to 6 GHz and can support a transmit

synthesis bandwidth up to 250 MHz, as well as a receiver

bandwidth up to 100 MHz.

The AD9371 provides three receiver inputs with limited

bandwidth (20 MHz) to monitor signals on other channels of

interest. These receivers, commonly referred to as sniffer

receivers (SnRxs), can be matched to different frequency range

antennae to monitor a wider spectrum during normal operation

in a more narrow band. The independent synthesizer associated

with these receivers allows the receivers to operate on different

frequency channels during normal transmit/receive operation.

An additional pair of receiver channels can be used as dedicated

observation receivers used to monitor the transmitter channels.

These receivers provide the same bandwidth and gain capability

as the main signal channel receivers, but are dedicated for use as

monitors for transmitter performance. These receivers provide

a feedback path to implement calibration and error correction

algorithms on the transmit data.

All signal data transfers are accomplished using a JESD204B

high speed serial interface with eight separate lanes. Four lanes

are dedicated as inputs to the transmitter system and four lanes

are configurable to serve as outputs for the receiver system.

When one or two main signal chain receivers are active and an

observation/sniffer receiver is active, the main signal chain

receivers can be assigned one or two receiver lanes, and the

observation/sniffer receiver can also be assigned only one or

two lanes. Note that only one observation receiver or sniffer

receiver can be operational at any given time, but all four lanes

can be assigned to that channel or shared between this channel

and the active signal chain receivers.

A serial peripheral interface (SPI) transmits and receives

control information between the device and a baseband

processor. All software control is communicated via this

interface. There is also a control interface that utilizes GPIO

lines to provide hardware control to and from the device. These

pins can be configured to provide dedicated sets of functions for

different application scenarios. Some GPIOs are intended for

digital control, while others are supplied by a 3.3 V analog

supply for use in controlling external analog components. There

are also ten auxiliary digital to analog converters (DACs), known as

auxiliary DACs, that can be muxed with 3.3 V GPIO pins to be

used as control voltage sources for other devices requiring variable

control voltages. Included in this block is a set of three low

speed auxiliary analog to digital converters (ADCs) that

monitor external voltages of interest to system operation.

Figure 1 shows a block diagram of AD9371. Software control of

each block is described in the following sections of this user

guide. Note that all software code is taken from the API that is

supplied with the AD9371. References to Mykonos in the API

refer to the Analog Devices development name for the AD9371

family of devices.

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