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Single Root I/O Virtualization and
Sharing Specification
Revision 1.0
1
September 11
January 20, 20072010
SINGLE ROOT I/O VIRTUALIZATION AND SHARING SPECIFICATION, REV. 1.10
3
Revision Revision History Date
1.0 Initial release. 9/11/2007
1.1
Corrected errata and added updates to reflect changes
associated with the PCI Express Base Specification,
Revision 2.1.
1/20/2010
PCI-SIG
®
disclaims all warranties and liability for the use of this document and the information
contained herein and assumes no responsibility for any errors that may appear in this document, nor
does PCI-SIG make a commitment to update the information contained herein.
Contact the PCI-SIG office to obtain the latest revision of the specification.
Questions regarding this document or membership in PCI-SIG may be forwarded to:
Membership Services
http://www.pcisig.com
E-mail: administration@pcisig.com
Phone: 503-619-0569
Fax: 503-644-6708
Technical Support
techsupp@pcisig.com
DISCLAIMER
This document is provided “as is” with no warranties whatsoever, including any warranty of
merchantability, non-infringement, fitness for any particular purpose, or any warranty otherwise
arising out of any proposal, specification, or sample. PCI-SIG disclaims all liability for infringement
of proprietary rights, relating to use of information in this specification. No license, express or
implied, by estoppel or otherwise, to any intellectual property rights is granted herein.
PCI Express, PCIe, PCI-X, PCI, and PCI-SIG are trademarks of PCI-SIG.
All other product names are trademarks, registered trademarks, or service marks of their respective
owners.
Copyright © 2007-2010
PCI-SIG
All rights reserved.
SINGLE ROOT I/O VIRTUALIZATION AND SHARING SPECIFICATION, REV. 1.10
4
Contents
OBJECTIVE OF THE SPECIFICATION................................................................................. 9
DOCUMENT ORGANIZATION................................................................................................ 9
DOCUMENTATION CONVENTIONS..................................................................................... 9
TERMS AND ABBREVIATIONS............................................................................................ 10
REFERENCE DOCUMENTS................................................................................................... 11
1. ARCHITECTURAL OVERVIEW
................................................................................... 12
1.1. PCI TECHNOLOGIES INTEROPERABILITY........................................................................ 26
2. INITIALIZATION AND RESOURCE ALLOCATION ................................................ 29
2.1. SR-IOV RESOURCE DISCOVERY.................................................................................... 29
2.1.1. Configuring SR-IOV Capabilities......................................................................... 29
2.1.2. VF Discovery ........................................................................................................ 30
2.1.3. Function Dependency Lists................................................................................... 33
2.1.4. Interrupt Resource Allocation............................................................................... 33
2.2. RESET MECHANISMS...................................................................................................... 33
2.2.1. Conventional Reset ............................................................................................... 33
2.2.2. FLR That Targets a VF......................................................................................... 34
2.2.3. FLR That Targets a PF......................................................................................... 34
2.3. IOV RE-INITIALIZATION AND REALLOCATION............................................................... 34
2.4. VF MIGRATION.............................................................................................................. 34
2.4.1. Initial VF State...................................................................................................... 35
2.4.2. VF Migration State Transitions............................................................................ 35
3. CONFIGURATION
............................................................................................................ 39
3.1. O
VERVIEW ..................................................................................................................... 39
3.2. C
ONFIGURATION SPACE................................................................................................. 39
3.3. SR-IOV EXTENDED CAPABILITY................................................................................... 39
3.3.1. SR-IOV Extended Capability Header (00h).......................................................... 42
3.3.2. SR-IOV Capabilities (04h)
.................................................................................... 42
3.3.3. SR-IOV Control (08h)........................................................................................... 45
3.3.4. SR-IOV Status (0Ah)
............................................................................................. 48
3.3.5. InitialVFs (0Ch).................................................................................................... 48
3.3.6. TotalVFs (0Eh)...................................................................................................... 48
3.3.7. NumVFs (10h)
....................................................................................................... 50
3.3.8. Function Dependency Link (12h).......................................................................... 50
3.3.9. First VF Offset (14h)
............................................................................................. 52
3.3.10. VF Stride (16h)
..................................................................................................... 52
3.3.11. VF Device ID (1Ah) .............................................................................................. 53
3.3.12. Supported P
age Sizes (1Ch).................................................................................. 53
SINGLE ROOT I/O VIRTUALIZATION AND SHARING SPECIFICATION, REV. 1.10
5
3.3.13. System Page Size (20h)......................................................................................... 53
3.3.14. VF BAR0, VF BAR1, … VF BAR5 (24h ... 38h).................................................... 54
3.3.15. VF Migration State Array Offset (3Ch) ................................................................ 55
3.4. PF/VF
CONFIGURATION SPACE HEADER ....................................................................... 58
3.4.1. Type 0 Configuration Space Header..................................................................... 59
3.5. PCI
EXPRESS CAPABILITY ............................................................................................. 63
3.5.1. PCI Express Capability List Register (Offset 00h)............................................... 65
3.5.2. PCI Express Capabilities Register (Offset 02h) ................................................... 65
3.5.3. Device Capabilities Register (Offset 04h) ............................................................ 66
3.5.4. Device Control Register (Offset 08h) ................................................................... 67
3.5.5. Device Status Register (Offset 0Ah)...................................................................... 68
3.5.6. Link Capabilities Register (Offset 0Ch)................................................................ 70
3.5.7. Link Control Register (Offset 10h) ....................................................................... 70
3.5.8. Link Status Register (Offset 12h).......................................................................... 73
3.5.9. Device Capabilities 2 Register (Offset 24h) ......................................................... 73
3.5.10. Device Control 2 Register (Offset 28h) ................................................................ 75
3.5.11. Device Status 2 Register (Offset 2Ah)................................................................... 75
3.5.12. Link Capabilities 2 Register (Offset 2Ch)............................................................. 75
3.5.13. Link Control 2 Register (Offset 30h) .................................................................... 75
3.5.14. Link Status 2 Register (Offset 32h)....................................................................... 75
3.6. PCI STANDARD CAPABILITIES ....................................................................................... 76
3.6.1. VPD Capability..................................................................................................... 76
3.7. PCI EXPRESS EXTENDED CAPABILITIES......................................................................... 77
3.7.1. Virtual Channel/MFVC......................................................................................... 78
3.7.2. Access Control Services (ACS) Extended Capability ........................................... 78
3.7.3. Alternative Routing ID Interpretation Extended Capability (ARI)....................... 80
3.7.4. Address Translation Services Extended Capability (ATS).................................... 80
3.7.5. MR-IOV................................................................................................................. 81
3.7.6. Multicast ............................................................................................................... 81
3.7.7. Page Request Interface (PRI) ............................................................................... 82
3.7.8. Dynamic Power Allocation (DPA)
........................................................................ 82
3.7.9. TLP Processing Hint (TPH).................................................................................. 83
4. ERROR H
ANDLING......................................................................................................... 84
4.1. B
ASELINE ERROR REPORTING........................................................................................ 84
4.2. ADVANCED ERROR REPORTING ..................................................................................... 85
4.2.1. VF Header Log ..................................................................................................... 85
4.2.2. Advanced Error Reporting Capability
.................................................................. 86
4.2.3. Advanced Error Reporting Extended Capability Header (Offset 00h)................. 87
4.2.4. Uncorrectable Error Status Register (Offset 04h)................................................ 88
4.2.5. Uncorrectable Error Mask Register (Offset 08h)
................................................. 88
4.2.6. Uncorrectable Error Severity Register (Offset 0Ch)............................................ 89
4.2.7. Correctable Error Status Register (Offset 10h)
.................................................... 90
4.2.8. Correctable Error Mask Register (Offset 14h)..................................................... 90
4.2.9. Advanced Error Capabilities and Control Register (Offset 18h)
......................... 91
4.2.10. Header Log Register (Offset 1Ch)
........................................................................ 91
4.2.11. Root Error Command Register (Offset 2Ch)
........................................................ 92
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