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MPC8379E PowerQUICC™ II Pro
Integrated Host Processor
Family Reference Manual
Supports
MPC8379E
MPC8379
MPC8378E
MPC8378
MPC8377E
MPC8377
MPC8379ERM
Rev. 1
2/2009
Document Number: MPC8379ERM
Rev. 1, 2/2009
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MPC8379E PowerQUICC II Pro Integrated Host Processor Family Reference Manual, Rev. 1
Freescale Semiconductor iii
Contents
Paragraph
Number Title
Page
Number
Co nt ents
About This Book
Audience .......................................................................................................................... ciii
Organization..................................................................................................................... ciii
Suggested Reading............................................................................................................cvi
General Information......................................................................................................cvi
Related Documentation.................................................................................................cvi
Conventions ......................................................................................................................cvi
Signal Conventions..........................................................................................................cvii
Acronyms and Abbreviations ........................................................................................ cviii
Chapter 1
Overview
1.1 MPC8379E Family Product Distinctions ........................................................................ 1-1
1.2 MPC8379E PowerQUICC II Pro Processor Overview ................................................... 1-1
1.3 MPC8379E Architecture Overview................................................................................. 1-9
1.3.1 Power Architecture Core ............................................................................................. 1-9
1.3.2 Security Engine......................................................................................................... 1-12
1.3.3 Dual DDR Memory Controllers ................................................................................ 1-12
1.3.4 Dual Enhanced Three-Speed Ethernet Controllers.................................................... 1-13
1.3.5 Enhanced Secure Digital Host Controller (eSDHC).................................................. 1-14
1.3.6 SerDes PHY............................................................................................................... 1-14
1.3.7 PCI Controller............................................................................................................ 1-15
1.3.7.1 PCI Bus Arbitration Unit...................................................................................... 1-15
1.3.8 Universal Serial Bus (USB) 2.0................................................................................. 1-16
1.3.8.1 USB Dual-Role Controller .................................................................................... 1-17
1.3.9 Enhanced Local Bus Controller (eLBC).................................................................... 1-17
1.3.10 Integrated Programmable Interrupt Controller (IPIC)...............................................1-19
1.3.11 Dual I
2
C Interfaces .................................................................................................... 1-19
1.3.12 DMA Controller......................................................................................................... 1-20
1.3.13 Dual Universal Asynchronous Receiver/Transmitter (DUART)............................... 1-21
1.3.14 Serial Peripheral Interface (SPI)................................................................................ 1-21
1.3.15 System Timers ........................................................................................................... 1-22
1.4 Applications................................................................................................................... 1-22
Chapter 2
Memory Map
MPC8379E PowerQUICC II Pro Integrated Host Processor Family Reference Manual, Rev. 1
iv Freescale Semiconductor
Contents
Paragraph
Number Title
Page
Number
2.1 Internal Memory Mapped Registers ................................................................................ 2-1
2.2 Accessing IMMR Memory From the Local Processor.................................................... 2-1
2.3 IMMR Address Map........................................................................................................ 2-1
Chapter 3
Signal Descriptions
3.1 Signals Overview.............................................................................................................3-1
3.2 Configuration Signals Sampled at Reset ....................................................................... 3-30
3.3 Output Signal States During Reset ................................................................................ 3-30
Chapter 4
Reset, Clocking, and Initialization
4.1 External Signals ............................................................................................................... 4-1
4.1.1 Reset Signals................................................................................................................4-1
4.1.2 Clock Signals ............................................................................................................... 4-3
4.2 Functional Description..................................................................................................... 4-4
4.2.1 Reset Operations.......................................................................................................... 4-4
4.2.1.1 Reset Causes ............................................................................................................ 4-4
4.2.1.2 Reset Actions ........................................................................................................... 4-5
4.2.2 Power-On Reset Flow.................................................................................................. 4-6
4.2.3 Hard Reset Flow .......................................................................................................... 4-8
4.2.4 Soft Reset Flow............................................................................................................4-9
4.3 Reset Configuration ......................................................................................................... 4-9
4.3.1 Reset Configuration Signals ...................................................................................... 4-10
4.3.1.1 Reset Configuration Word Source ......................................................................... 4-10
4.3.1.2 CLKIN Division .................................................................................................... 4-11
4.3.1.3 LBMUX Configuration ......................................................................................... 4-11
4.3.1.4 Selecting Reset Configuration Input Signals......................................................... 4-11
4.3.2 Reset Configuration Words........................................................................................ 4-12
4.3.2.1 Reset Configuration Word Low Register (RCWLR)............................................. 4-13
4.3.2.1.1 System PLL VCO Division ............................................................................... 4-14
4.3.2.1.2 System PLL Configuration................................................................................ 4-15
4.3.2.2 Reset Configuration Word High Register (RCWHR)............................................ 4-16
4.3.2.2.1 PCI Host/Agent Configuration .......................................................................... 4-18
4.3.2.2.2 Boot Memory Space (BMS).............................................................................. 4-18
4.3.2.2.3 Boot Sequencer Configuration .......................................................................... 4-19
4.3.2.2.4 Boot ROM Location .......................................................................................... 4-19
4.3.2.2.5 Boot from SPI.................................................................................................... 4-20
4.3.2.2.6 eTSEC1 Mode ................................................................................................... 4-21
MPC8379E PowerQUICC II Pro Integrated Host Processor Family Reference Manual, Rev. 1
Freescale Semiconductor v
Contents
Paragraph
Number Title
Page
Number
4.3.2.2.7 eTSEC2 Mode ................................................................................................... 4-22
4.3.2.2.8 e300 Core True Little-Endian............................................................................ 4-22
4.3.2.2.9 LDP Configuration ............................................................................................ 4-23
4.3.3 Loading the Reset Configuration Words ................................................................... 4-23
4.3.3.1 Loading from Local Bus........................................................................................ 4-23
4.3.3.1.1 Local Bus Controller Setting ............................................................................. 4-24
4.3.3.2 Loading from I2C EEPROM................................................................................. 4-25
4.3.3.2.1 Using the Boot Sequencer Reset Configuration................................................ 4-26
4.3.3.2.2 EEPROM Calling Address ................................................................................ 4-26
4.3.3.2.3 EEPROM Data Format in Reset Configuration Mode ...................................... 4-26
4.3.3.2.4 Reset Configuration Load Fail .......................................................................... 4-29
4.3.3.3 Default Reset Configuration Words....................................................................... 4-29
4.3.3.3.1 Examples for Hard-Coded Reset Configuration Words Usage ......................... 4-31
4.4 Clocking ........................................................................................................................4-32
4.4.1 Clocking in PCI Host Mode....................................................................................... 4-32
4.4.1.1 PCI Clock Outputs (PCI_CLK_OUT[0:4])...........................................................4-33
4.4.2 Clocking In PCI Agent Mode .................................................................................... 4-33
4.4.3 System Clock Domains.............................................................................................. 4-33
4.5 Memory Map/Register Definitions................................................................................ 4-34
4.5.1 Reset Configuration Register Descriptions................................................................ 4-34
4.5.1.1 Reset Configuration Word Low Register (RCWLR)............................................. 4-35
4.5.1.2 Reset Configuration Word High Register (RCWHR)............................................ 4-35
4.5.1.3 Reset Status Register (RSR) .................................................................................. 4-35
4.5.1.4 Reset Mode Register (RMR) ................................................................................. 4-37
4.5.1.5 Reset Protection Register (RPR) ........................................................................... 4-37
4.5.1.6 Reset Control Register (RCR) ............................................................................... 4-38
4.5.1.7 Reset Control Enable Register (RCER)................................................................. 4-39
4.5.2 Clock Configuration Registers................................................................................... 4-39
4.5.2.1 System PLL Mode Register (SPMR) .................................................................... 4-39
4.5.2.2 Output Clock Control Register (OCCR)................................................................ 4-41
4.5.2.3 System Clock Control Register (SCCR)................................................................ 4-42
Chapter 5
System Configuration
5.1 Introduction...................................................................................................................... 5-1
5.2 Local Memory Map Overview and Example .................................................................. 5-1
5.2.1 Address Translation and Mapping............................................................................... 5-3
5.2.2 Window into Configuration Space............................................................................... 5-4
5.2.3 Local Access Windows................................................................................................ 5-4
5.2.3.1 Local Access Register Memory Map ...................................................................... 5-5
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- soulphone2013-10-24非常好,是全的版本,不是简洁版本。
- pangxing1272012-07-19只是大致了解一下特性
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