交通灯程序（verilog语言）

    `timescale 100ns / 1ps
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// Company: 
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// Create Date:    14:46:09 04/02/09
// Design Name:    
// Module Name:    JTD
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// Tool versions:  
// Description:
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// Dependencies:
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// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
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module traffic (clock, reset, light);
input clock, reset, ; 
output light;  
parameter 
  st0 = 0, st1 = 1, st2 = 2, st3 = 3;
reg [2:0] state, nxstate ; 
reg[8:0] light; 

always @(posedge clock or posedge reset)
begin