This directory contains 8051 firmware for the Cypress Semiconductor EZ-USB FX2
chip.
The purpose of this code is to demonstrate how to utilize EZUSB FX2 Slave FIFOs.
It configures FX2 as follows:
01). EP2 512 2x BULK OUT - 8-bit async AUTO mode
02). EP4 512 2x BULK IN - 8-bit async AUTO mode
03). EP6 512 2x BULK OUT - 8-bit async AUTO mode
04). EP8 512 2x BULK IN - 8-bit async AUTO mode
05). FIFO strobes and flags are all active low
06). FLAGA - fixed EP2EF
07). FLAGB - fixed EP4FF
08). FLAGC - fixed EP6EF
09). FLAGD - fixed EP8FF
10). SLCS isn't being used
11). FX2 can't signal zerolen OUT token to the master
.....from the ext. master (xmaster in this case is FX in GPIF mode, CY3671 DK)
01). 512 byte buffer for EP2 OUT -> EP6 IN data
02). 512 byte buffer for EP4 OUT -> EP8 IN data
03). xmaster just loops back the data
05). xmaster supervises "not empty" / "not full" / "pktend" status
06). peripheral interface functions in 8-bit async mode
.....from "the user":
01). CY3681 DK is connected to a HS host controller
02). EP2 512 2x BULK OUT data is looped back to EP6 512 2x BULK IN
03). EP4 512 2x BULK OUT data is looped back to EP8 512 2x BULK IN
04). EZUSB Control Panel to download "FX2" example firmware
05). EZUSB Control Panel to xfr OUT/IN tokens via CY3681 DK
The "tcxmaster.hex" file loads into internal memory.
...issue "build -i" at the command prompt...
This example is for illustrative purpose(s) and unless you have an ext. master
that emulates the testing environment this example won't actually produce
expected results when downloaded via Control Panel. The external master in this
case is EZUSB FX (CY3671 DK) running in GPIF master mode
Some thoughts about xmaster pseudo code:
========================================
Burst Read from slave EP2
=========================
if endp "not empty event", (EP2EF=1)
init localbuf ef, ff, bc
while localbuf not full
if slave empty event
break
else
enqueue(localbuf, currentbyte)
end while
...turn around and fire data back out to FX2
Burst Write to slave EP6
========================
if endp "not full" (EP6FF=1)
while localbuf not empty
if slave full event
break
else
dequeue(localbuf, currentbyte)
end while
...now for the other paired loopback endp's
Burst Read from slave EP4
=========================
if endp "not empty event", (EP4EF=1)
init localbuf ef, ff, bc
while localbuf not full
if slave empty event
break
else
enqueue(localbuf, currentbyte)
end while
...turn around and fire data back out to FX2
Burst Write to slave EP8
========================
if endp "not full" (EP8FF=1)
while localbuf not empty
if slave full event
break
else
dequeue(localbuf, currentbyte)
end while
Below is an example of the physical interface between FX2 in slave fifo mode
and FX in GPIF master mode. This information is only useful as a reference
study. If you're not familiar with the GPIF feature EZUSB then perhaps it would
be best to just think about it as a programmable state machine that can be
programmed to meet almost any parallel peripheral interface bus timing...
...In addition, FX has a pair of interface fifo(s) (AFIFO/BFIFO) that the GPIF
uses during burst transactions...
A little about the physical interface:
======================================
- testing flags during burst reads...
* FX2 fadr assert to flags valid, >9.1nsec
* FX async RDY setup time, >62.4nsec
- testing flags during burst writes...
* FX2 fadr assert to flags valid, >9.1nsec
* FX async RDY setup time, >62.4nsec
EP2RdAs: (11 cycles * 20.8nsec * 512 bytes/pkt ~ 117usec/pkt until GPIFDONE)
* S0: wait 83.2nsec, handle async RDYn (62.4nsec)
and EP2EF setup time (70nsec)
and SLRD pulse width high (50nsec)
* S1: test EP2EF, if empty jump S6 (signal "pre-abort") else S2
* S2: test FIFOFlag (AINPFPIN), throttle on AINPFPIN (infull)
* S3: assert SLRD/SLOE for ~62.4nsec to meet pulse width low (50nsec)
and turn-on to data valid (7.5nsec)
* S4: keep SLRD/SLOE asserted and sample data
* S5: loop S0, this waveform never terminates "naturally", using TC=1 scheme
* S6: EP2EF detected, signal "pre-abort" to 8051, loop S6 until 8051 ABORT
* S7: IDLE, not used in this scheme
EP6WrAs: (11 cycles * 20.8nsec * 512 bytes/pkt ~ 117usec/pkt until GPIFDONE)
* S0: wait 83.2nsec, handle async RDYn (62.4nsec)
and EP6FF setup time (70nsec)
and SLWR pulse width high (70nsec)
* S1: test FIFOFlag (AOUTPFPIN), throttle on AOUTPFPIN (outempty)
* S2: test EP6FF, if full jump S0 (wait for host to drain the data) else S3
and drive the data to meet SLWR to data setup time (2.7nsec)
* S3: assert SLWR for 62.4nsec to meet pulse width low (50nsec)
and drive the data
* S4: drive the data to meet data to SLWR hold time (2.7nsec)
* S5: inc. AFIFO data pointer, "NextData"
and loop S0, this waveform never terminates "naturally", using TC=1 scheme
* S6: not used in this waveform
* S7: IDLE, not used in this scheme
EP4RdAs: (11 cycles * 20.8nsec * 512 bytes/pkt ~ 117usec/pkt until GPIFDONE)
* S0: wait 83.2nsec, handle async RDYn (62.4nsec)
and EP2EF setup time (70nsec)
and SLRD pulse width high (50nsec)
* S1: test EP4EF, if empty jump S6 (signal "pre-abort") else S2
* S2: test FIFOFlag (BINPFPIN), throttle on BINPFPIN (infull)
* S3: assert SLRD/SLOE for 62.4nsec to meet pulse width low (50nsec)
and turn-on to data valid (7.5nsec)
* S4: keep SLRD/SLOE asserted and sample data
* S5: loop S0, this waveform never terminates "naturally", using TC=1 scheme
* S6: EP4EF detected, signal "pre-abort" to 8051, loop S6 until 8051 ABORT
* S7: IDLE, not used in this scheme
EP8WrAs: (11 cycles * 20.8nsec * 512 bytes/pkt ~ 117usec/pkt until GPIFDONE)
* S0: wait 83.2nsec, handle async RDYn (62.4nsec)
and EP6FF setup time (70nsec)
and SLWR pulse width high (70nsec)
* S1: test FIFOFlag (AOUTPFPIN), throttle on AOUTPFPIN (outempty)
* S2: test EP6FF, if full jump S0 (wait for host to drain the data) else S3
and drive the data to meet SLWR to data setup time (2.7nsec)
* S3: assert SLWR for 62.4nsec to meet pulse width low (50nsec)
and drive the data
* S4: drive the data to meet data to SLWR hold time (2.7nsec)
* S5: inc. AFIFO data pointer, "NextData"
and loop S0, this waveform never terminates "naturally", using TC=1 scheme
* S6: not used in this waveform
* S7: IDLE, not used in this scheme
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NiosII的USB设计教程及USB2.0接口设计实例文件包 (484个子文件)
fifo.__i 48B
_info 621B
_info 543B
_info 540B
dscr.a51 8KB
Test.aps 22KB
Test.aps 21KB
Test.aps 21KB
ezusbsys.aps 17KB
verilog.asm 23KB
verilog.asm 15KB
verilog.asm 12KB
verilog.asm 10KB
verilog.asm 9KB
verilog.asm 9KB
rd_wr_fifo.qsf.bak 6KB
zd_ad.qsf.bak 5KB
asyn_rd.qsf.bak 5KB
wr_fifo.qsf.bak 4KB
slavefifo_Uv2.Bak 2KB
slavefifo_Opt.Bak 1KB
build.bat 2KB
MakeDrvr.bat 337B
ezusbsys.c 152KB
fw.c 13KB
fifo.c 10KB
asyn_rd.cmp.cdb 128KB
asyn_rd.sgdiff.cdb 41KB
asyn_rd.map.cdb 40KB
rd_wr_fifo.cmp.cdb 33KB
rd_wr_fifo.pre_map.cdb 17KB
rd_wr_fifo.rtlv_sg.cdb 17KB
rd_wr_fifo.(0).cnf.cdb 14KB
asyn_rd.(34).cnf.cdb 11KB
asyn_rd.(54).cnf.cdb 10KB
rd_wr_fifo.sgdiff.cdb 9KB
rd_wr_fifo.map.cdb 9KB
asyn_rd.(1).cnf.cdb 9KB
asyn_rd.(43).cnf.cdb 8KB
wr_fifo.cmp.cdb 7KB
asyn_rd.(5).cnf.cdb 6KB
asyn_rd.(52).cnf.cdb 5KB
asyn_rd.(2).cnf.cdb 5KB
asyn_rd.(55).cnf.cdb 5KB
asyn_rd.(62).cnf.cdb 4KB
wr_fifo.pre_map.cdb 4KB
asyn_rd.(51).cnf.cdb 4KB
wr_fifo.rtlv_sg.cdb 4KB
asyn_rd.(53).cnf.cdb 4KB
wr_fifo.(0).cnf.cdb 3KB
asyn_rd.(41).cnf.cdb 3KB
asyn_rd.(42).cnf.cdb 3KB
asyn_rd.(3).cnf.cdb 3KB
asyn_rd.(40).cnf.cdb 3KB
asyn_rd.(59).cnf.cdb 3KB
asyn_rd.(6).cnf.cdb 3KB
asyn_rd.(35).cnf.cdb 3KB
asyn_rd.(4).cnf.cdb 3KB
asyn_rd.(14).cnf.cdb 3KB
asyn_rd.(44).cnf.cdb 3KB
asyn_rd.(61).cnf.cdb 3KB
asyn_rd.(58).cnf.cdb 3KB
asyn_rd.(17).cnf.cdb 2KB
wr_fifo.map.cdb 2KB
asyn_rd.(37).cnf.cdb 2KB
asyn_rd.(45).cnf.cdb 2KB
wr_fifo.sgdiff.cdb 2KB
asyn_rd.(57).cnf.cdb 2KB
asyn_rd.(47).cnf.cdb 2KB
asyn_rd.(31).cnf.cdb 2KB
asyn_rd.(15).cnf.cdb 2KB
asyn_rd.(56).cnf.cdb 2KB
asyn_rd.(29).cnf.cdb 2KB
asyn_rd.(39).cnf.cdb 2KB
asyn_rd.(33).cnf.cdb 2KB
asyn_rd.(18).cnf.cdb 2KB
asyn_rd.(9).cnf.cdb 1KB
asyn_rd.(12).cnf.cdb 1KB
asyn_rd.(10).cnf.cdb 1KB
asyn_rd.(21).cnf.cdb 1KB
asyn_rd.(7).cnf.cdb 1KB
asyn_rd.(0).cnf.cdb 1KB
asyn_rd.pre_map.cdb 1KB
asyn_rd.(32).cnf.cdb 1KB
asyn_rd.rtlv_sg.cdb 1KB
asyn_rd.(11).cnf.cdb 1KB
asyn_rd.(25).cnf.cdb 1KB
asyn_rd.(24).cnf.cdb 1KB
asyn_rd.(16).cnf.cdb 1KB
asyn_rd.(30).cnf.cdb 1KB
asyn_rd.(13).cnf.cdb 1KB
asyn_rd.(38).cnf.cdb 1KB
asyn_rd.(20).cnf.cdb 1KB
asyn_rd.(49).cnf.cdb 1KB
asyn_rd.(50).cnf.cdb 1KB
asyn_rd.(60).cnf.cdb 1KB
asyn_rd.(36).cnf.cdb 1012B
asyn_rd.(19).cnf.cdb 946B
asyn_rd.(22).cnf.cdb 935B
asyn_rd.(26).cnf.cdb 931B
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